NXP Semiconductors MPC5566, Reference Manual

Page: 980 / 1268

Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 20-55
Figure 20-33 shows the timing of the PCSS signal relative to PCS signals.
Figure 20-33. Peripheral Chip Select Strobe Timing
The delay between the assertion of the PCS x signals and the assertion of PCSS is selected by the PCSSCK
field in the DSPI x _CTAR based on the following formula:
At the end of the transfer the delay between PCSS negation and PCS x negation is selected by the PASC
field in the DSPI x _CTAR based on the following formula:
Table 20-27 shows an example of the computed t
PCSSCK
delay.
Table 20-28 shows an example of the computed the t
PASC
delay.
20.4.7 Transfer Formats
The SPI serial communication is controlled by the serial communications clock (SCK x ) signal and the
PCS x signals. The SCK x signal provided by the master device synchronizes shifting and sampling of the
data by the SIN x and SOUT x pins. The PCS x signals serve as enable signals for the slave devices.
When the DSPI is the bus master, the CPOL and CPHA bits in the DSPI clock and transfer attributes
registers (DSPI
x _CTAR n ) select the polarity and phase of the serial clock, SCK x . The polarity bit selects
the idle state of the SCK x . The clock phase bit selects if the data on SOUT x is valid before or on the first
SCK x edge.
Table 20-27. Peripheral Chip Select Strobe Assert Computation Example
PCSSCK Prescaler
f
SYS
Delay before Transfer
0b11 7 100 MHz 70.0 ns
Table 20-28. Peripheral Chip Select Strobe Negate Computation Example
PASC Prescaler
f
SYS
Delay after Transfer
0b11 7 100 MHz 70.0 ns
PCSS
PCSx
t
PCSSCK
t
PASC
tPCSSCK =
PCSSCK
×
f
SYS
1
tPASC =
PASC
×
f
SYS
1