NXP Semiconductors MPC5566, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
20-34 Freescale Semiconductor
The DSPI x _CTAR0–DSPI x _CTAR7 registers hold clock and transfer attributes. The manner in which a
CTAR is selected depends on the DSPI configuration (SPI, DSI, or CSI). The SPI configuration can select
which CTAR to use on a frame by frame basis by setting the CTAS field in the DSPI
x _PUSHR. The DSI
configuration statically selects which CTAR to use. In CSI configuration, priority logic determines if SPI
data or DSI data is transferred. The type of data transferred (whether DSI or SPI) dictates which CTAR the
CSI configuration uses. See
Section 20.3.2.3, “DSPI Clock and Transfer Attributes Registers 0–7
(DSPIx_CTARn) ,” for information on DSPI x _CTAR fields.
The 16-bit shift register in the master and the 16-bit shift register in the slave are linked by the SOUT x and
SIN x signals to form a distributed 32-bit register. When a data transfer operation is performed, data is
serially shifted a pre-determined number of bit positions. Because the registers are linked, data is
exchanged between the master and the slave; the data that was in the master’s shift register is now in the
shift register of the slave, and vice versa. At the end of a transfer, the TCF bit in the DSPI
x _SR is set to
indicate a completed transfer. Figure 20-17 illustrates how master and slave data is exchanged.
Figure 20-17. SPI and DSI Serial Protocol Overview
The DSPI has six peripheral chip select (PCS
x
) signals that are be used to select which of the slaves to
communicate with.
Transfer protocols and timing properties are shared by the three DSPI configurations; these properties are
described independently of the configuration in
Section 20.4.7, “Transfer Formats .” The transfer rate and
delay settings are described in section Section 20.4.6, “DSPI Baud Rate and Clock Delay Generation .”
See Section 20.4.10, “Power Saving Features ” for information on the power-saving features of the DSPI.
20.4.1 Modes of Operation
The DSPI modules have four available distinct modes:
• Master mode
• Slave mode
• Module disable mode
• Debug mode
Master, slave, and module disable modes are module-specific modes while debug mode is a
device-specific mode.
The module-specific modes are determined by bits in the DSPI x _MCR. Debug mode is a mode that the
entire device can enter in parallel with the DSPI being configured in one of its module-specific modes.
DSPI Master
Shift register
Baud rate generator
DSPI Slave
Shift register
SOUT x
SIN x
SOUT x SIN x
SCK x SCK x
PCS x SS