NXP Semiconductors MPC5566, Reference Manual

Page: 1255 / 1268

Calibration
MPC5566 Microcontroller Reference Manual, Rev. 2
B-4 Freescale Semiconductor
B.3 Device-Specific Information
The various address bus, data bus and bus control signals are sourced from different signals depending on
the MPC5500 device used, as detailed in the following sections.
B.3.1 MPC5566 Calibration Bus Implementation
The MPC5566 device has a set of external bus signals that are only used by the calibration bus. These
device signals are prefixed by CAL, and their use does not affect the usage modes and electrical loading
on the equivalent signals for the EBI.
B.4 Signals and Pads
The following sections detail the signal descriptions for the calibration bus.
B.4.1 CAL_CS[0:3] — Calibration Chip Selects 0 through 3
CAL_CS[ n ] is asserted by the master to indicate that this transaction is targeted for a particular calibration
memory bank.
The calibration chip selects are driven by the EBI. CAL_CS[ n ] is driven in the same clock as the assertion
of TS and valid address, and is kept valid until the cycle is terminated. Bus timing is identical to standard
EBI timing.
B.4.1.1 Number of Chip Selects and Maximum Memory Size
The trade-off between calibration chip selects and address lines is the same as the trade-off between
non-calibration chip selects and address lines for the 324 pin package.
B.4.2 Pad Ring
This section provides a list of the calibration pins and associated pad configuration registers (PCRs),
including links to the detailed PCR information for each pin or pin group.
Refer to Table B-1 for device signal names.
Table B-2. Maximum Memory Size According to Calibration Chip Selects
Maximum Memory Allocated for Calibration
Device 0 Device 2 Device 3
CAL_CS[0] only 4 MB
— —
CAL_CS[0] and
CAL_CS[2] 2 MB 2 MB
—
CAL_CS[0] and
CAL_CS[2:3] 1 MB 1 MB 1 MB