NXP Semiconductors MPC5566, Reference Manual

Page: 1055 / 1268

MPC5566 Microcontroller Reference Manual, Rev. 2
22-18 Freescale Semiconductor
The meaning of each mask bit is the following:
• Mask bit = 0: The corresponding incoming ID bit is a “don’t care.”
• Mask bit = 1: The corresponding ID bit is checked against the incoming ID bit, to see if a match
exists.
The Individual Rx Mask Registers are implemented in RAM, so they are not affected by reset and must be
explicitly initialized prior to any reception. Furthermore, they can only be accessed by the CPU while the
module is in freeze mode. Out of freeze mode, write accesses are blocked and read accesses return all 0s.
Furthermore, if the MBFEN bit in the MCR register is negated, any read or write operation to these
RXIMR
n registers results in access error.
22.3.3.6 Error Counter Register (CAN x _ECR)
CAN x _ECR has two 8-bit fields reflecting the value of two FlexCAN2 error counters: the transmit error
counter (TXECTR field) and receive error counter (RXECTR field)
.
The rules for increasing and
decreasing these counters are described in the CAN protocol and are completely implemented in the
FlexCAN2 module. Both counters are read only except in freeze mode, where they can be written by the
CPU.
Writing to the CAN x _ECR while in freeze mode is an indirect operation. The data is first written to an
auxiliary register, and then an internal request/acknowledge procedure across clock domains is executed.
This occurs internally without indication, except for the time delay required for the data write to the
register. Software can poll the register to verify that the data is written.
Address: Base + 0x0880–0x097F Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0
MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16
W
Reset
1
U U U U U U U U U U U U U U U U
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
MI15 MI14 MI13 MI12 MI11 MI10 MI9 MI8 MI7 MI6 MI5 MI4 MI3 MI2 MI1 MI0
W
Reset
1
U U U U U U U U U U U U U U U U
1
The ‘U’ indicates the value is undefined after reset.
Figure 22-7. RX Individual Mask Registers (CANx_RXIMR0 through CANx_RXIMR63)
Table 22-11. CANx_RXIMR0–CANx_RXIMR63 Field Descriptions
Field Description
0–2 Reserved.
3–13
MI28–MI18
Standard ID mask bits. These bits are the same mask bits for the standard and extended formats.
14–31
MI17–MI0
Extended ID mask bits. These bits are used to mask comparison only in extended format.