NXP Semiconductors MPC5566, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 20-53
20.4.6 DSPI Baud Rate and Clock Delay Generation
The SCK x frequency and the delay values for serial transfer are generated by dividing the system clock
frequency by a prescaler and a scaler with the option of doubling the baud rate.
Figure 20-32 shows conceptually how the SCK signal is generated.
Figure 20-32. Communications Clock Prescalers and Scalers
20.4.6.1 Baud Rate Generator
The baud rate is the frequency of the serial communication clock (SCK x ). The system clock is divided by
a baud rate prescaler (defined by DSPI x _CTAR[PBR]) and baud rate scaler (defined by
DSPI x _CTAR[BR]) to produce SCK x with the possibility of doubling the baud rate. The DBR, PBR, and
BR fields in the DSPI x _CTARs select the frequency of SCK x using the following formula:
Table 20-23 shows an example of a computed baud rate.
20.4.6.2 PCS to SCK Delay (t
CSC
)
The PCS x to SCK x delay is the length of time from assertion of the PCS x signal to the first SCK x edge.
See Figure 20-34 for an illustration of the PCS x to SCK x delay. The PCSSCK and CSSCK fields in the
DSPI x _CTAR n registers select the PCS x to SCK x delay, and the relationship is expressed by the following
formula:
Table 20-24 shows an example of the computed PCS to SCK delay.
Table 20-23. Baud Rate Computation Example
f
SYS
PBR
Prescaler
Value
BR
Scaler
Value
DBR
Value
Baud Rate
100 MHz 0b00 2 0b0000 2 0 25 Mb/sec
20 MHz 0b00 2 0b0000 2 1 10 Mb/sec
Table 20-24. PCS to SCK Delay Computation Example
PCSSCK
Prescaler
Value
CSSCK
Scaler
Value
f
SYS
PCS to SCK Delay
0b01 3 0b0100 32 100 MHz 0.96
μ
s
Prescaler
1
Scaler
1 + DBR
System clock SCKx
SCK baud rate
f
SYS
PBRPrescalerValue
----------------------------------------------------------
1 DBR +
BRScalerValue
--------------------------------------------
×
=
t
CSC
=
f
SYS
CSSCK
×
PCSSCK
1
×