MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
22-19
FlexCAN2 responds to any bus state as described in the protocol: transmitting, for example, an ‘error
active’ or ‘error passive’ flag, delaying its transmission start time (‘error passive’), and avoiding any
influence on the bus when in the bus off state. The following are the basic rules for FlexCAN2 bus state
transitions:
•
If the value of TXECTR or RXECTR increases to be greater than or equal to 128, the FLTCONF
field in the CAN
x
_ESR is updated to reflect the ‘error passive’ state.
•
If the FlexCAN2 state is ‘error passive,’ and either TXECTR or RXECTR decrements to a value
less than or equal to 127 while the other already satisfies this condition, the FLTCONF field in the
CAN
x
_ESR is updated to reflect the ‘error active’ state.
•
If the value of TXECTR increases to greater than 255, the FLTCONF field in the CAN
x
_ESR is
updated to reflect the bus off state, and can issue an interrupt. The value of TXECTR is then reset
to zero.
•
If FlexCAN2 is in the bus off state, then TXECTR is cascaded together with another internal
counter to count the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
TXECTR is reset to zero and counts in a manner where the internal counter counts 11 such bits and
then wraps around while incrementing the TXECTR. When TXECTR reaches the value of 128, the
FLTCONF field in CAN
x
_ESR is updated to be ‘error active’ and both error counters are reset to
zero. At any instance of dominant bit following a stream of less than 11 consecutive recessive bits,
the internal counter resets itself to zero without affecting the TXECTR value.
•
If during system start-up, only one node is operating, then its TXECTR increases in each message
it is trying to transmit, as a result of acknowledge errors (indicated by the ACKERR bit in
CAN
x
_ESR). After the transition to the ‘error passive’ state, the TXECTR does not increment
anymore by acknowledge errors. Therefore the device never goes to the bus off state.
•
If the RXECTR increases to a value greater than 127, it is not incremented further, even if more
errors are detected while being a receiver. At the next successful message reception, the counter is
set to a value between 119 and 127 to resume to ‘error active’ state.
22.3.3.7
Error and Status Register (CAN
x
_ESR)
CAN
x
_ESR reflects various error conditions, some general status of the device, and it is the source of two
interrupts to the CPU. The reported error conditions (bits 16–21) are those that occurred since the last time
the CPU read this register. The CPU read action clears BIT1ERR, BIT0ERR, ACKERR, CRCERR,
FRMERR, and STFERR. TXWRN, RXWRN, IDLE, TXRX, FLTCONF, BOFFINT, and ERRINT are
status bits.
Most bits in this register are read-only, except BOFFINT, ERRINT, TWRNINT, and RWRNINT which are
interrupt flags that can be cleared by writing 1 to them (writing 0 has no effect).
Address: Base + 0x001C
Access: User R/W
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RXECTR
TXECTR
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 22-8. Error Counter Register (CAN
x
_ECR)
Summary of Contents for MPC5566
Page 81: ...Introduction MPC5566 Microcontroller Reference Manual Rev 2 1 24 Freescale Semiconductor...
Page 135: ...Signal Description MPC5566 Microcontroller Reference Manual Rev 2 2 54 Freescale Semiconductor...
Page 189: ...Reset MPC5566 Microcontroller Reference Manual Rev 2 4 20 Freescale Semiconductor...
Page 603: ...Flash Memory MPC5566 Microcontroller Reference Manual Rev 2 13 38 Freescale Semiconductor...
Page 609: ...SRAM MPC5566 Microcontroller Reference Manual Rev 2 14 6 Freescale Semiconductor...
Page 1073: ...MPC5566 Microcontroller Reference Manual Rev 2 22 36 Freescale Semiconductor...
Page 1185: ...Nexus MPC5566 Microcontroller Reference Manual Rev 2 25 92 Freescale Semiconductor...
