NXP Semiconductors MPC5566, Reference Manual

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Introduction
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 1-17
The BAM reads the reset configuration halfword (RCHW) from flash memory (either internal or external)
to configure the device hardware. The MMU is then configured for all resources and maps all physical
addresses to logical addresses with the minimum address translation, to allow application boot code to
execute as either Classic Power Architecture Book E code (default) or as Freescale VLE code.
1.5.13 Enhanced Management Input/Output System (eMIOS)
The enhanced modular I/O system (eMIOS) module generates or measures time events. A unified channel
(UC) module provides a consistent interface to a superset of all the MIOS channel functionality. This
allows more flexibility to program each unified channel for different functions in different applications.
To identify up to two timed events, each UC uses two comparators, a time base selector, and registers. This
structure can produce match events to measure or generate a waveform. Alternatively, input events can
capture the time base, allowing measurement of an input signal.
1.5.14 Enhanced Time Processing Unit (eTPU)
The enhanced time processing unit (eTPU) is an enhanced coprocessor designed for timing control.
Operating in parallel with the host CPU, the eTPU processes instructions and real-time input events,
performs output waveform generation, and accesses shared data without host intervention. Consequently,
for each timer event, the CPU setup and service times are minimized or eliminated. In the MCU, the TPU
engine is combined with shared instruction and data RAM to form a powerful time processing subsystem.
The MPC5566 has two eTPU engines. You can use the high-level assembler and compiler, along with the
eTPU documentation set, to develop customized eTPU functions. The eTPU supports several features of
older TPU versions, making it easy to port earlier application versions.
1.5.15 Enhanced Queued A/D Converter (eQADC)
The enhanced queued analog to digital converter (eQADC) module provides accurate and fast conversions
for a wide range of applications. The eQADC provides a parallel interface to two on-chip analog to digital
converters (ADCs), and a single master-to-single slave serial interface to an off-chip external device. The
two on-chip ADCs are designed to access all the analog channels.
The eQADC transfers commands from multiple command FIFOs (CFIFOs) to the on-chip ADCs or to the
external device. The module can also receive data from the on-chip ADCs or from an off-chip external
device into multiple result FIFOs (RFIFOs) in parallel, independently of the CFIFOs. The eQADC
supports software and external hardware triggers from other modules to initiate transfers of commands
from the CFIFOs to the on-chip ADCs or to the external device. It also monitors the fullness of CFIFOs
and RFIFOs, and accordingly generates eDMA or interrupt requests to control data movement between the
FIFOs and the system memory, which is external to the eQADC.
1.5.16 Deserial/Serial Peripheral Interface (DSPI)
The deserial serial peripheral interface (DSPI) module provides a synchronous serial interface for
communication between the MCU and external devices. The DSPI supports pin-count reduction through