NXP Semiconductors MPC5566, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 20-35
20.4.1.1 Master Mode
In master mode the DSPI can initiate communications with peripheral devices. The DSPI operates as bus
master when the MSTR bit in the DSPI
x _MCR is set. The serial communications clock (SCK) is
controlled by the master DSPI. All three DSPI configurations are valid in master mode.
In SPI configuration, master mode transfer attributes are controlled by the SPI command in the current TX
FIFO entry. The CTAS field in the SPI command selects which of the eight DSPI
x _CTARs are used to set
the transfer attributes. Transfer attribute control is on a frame by frame basis.
See Section 20.4.3, “Serial Peripheral Interface (SPI) Configuration ” for more details.
In DSI configuration, master mode transfer attributes are controlled by the DSPI x _DSCIR. A detailed
description of the DSPI x _DSCIR is located in Section 20.3.2.10, “DSPI DSI Configuration Register
(DSPIx_DSICR) .” The DSISCTAS field in the DSPI x _DSICR selects which of the DSPI x _CTARs are
used to set the transfer attributes. Transfer attributes are set up during initialization and must not be
changed between frames.
See Section 20.4.4, “Deserial Serial Interface (DSI) Configuration ,” for more details.
The CSI configuration is only available in master mode. In CSI configuration, the DSI data is transferred
using DSI configuration transfer attributes and SPI data is transferred using the SPI configuration transfer
attributes. In order for the bus slave to distinguish between DSI and SPI frames, the transfer attributes for
the two types of frames must utilize different peripheral chip select signals.
See Section 20.4.5, “Combined Serial Interface (CSI) Configuration ,” for details.
20.4.1.2 Slave Mode
In slave mode the DSPI responds to transfers initiated by an SPI master. The DSPI operates as bus slave
when the MSTR bit in the DSPI
x _MCR is negated. The DSPI slave is selected by a bus master by having
the slave’s SS asserted. In slave mode the SCK is provided by the bus master. All transfer attributes are
controlled by the bus master, except the clock polarity, clock phase and the number of bits to transfer which
must be configured in the DSPI slave to communicate correctly.
The SPI and DSI configurations are valid in slave mode. CSI configuration is not available in slave mode.
In SPI slave mode the slave transfer attributes are set in the DSPI
x _CTAR0. In DSI slave mode the slave
transfer attributes are set in the DSPI x _CTAR1. In slave mode, for both SPI and DSI configurations, data
is transferred MSB first. The LSBFE field of the associated CTAR is ignored.
20.4.1.3 Module Disable Mode
The module disable mode is used for MCU power management. The clock to the non-memory mapped
logic in the DSPI is stopped while in module disable mode. The DSPI enters the module disable mode
when the MDIS bit in DSPI
x _MCR is set.
See Section 20.4.10, “Power Saving Features ,” for more details on the module disable mode.