NXP Semiconductors MPC5566, Reference Manual

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Interrupt Controller (INTC)
MPC5566 Microcontroller Reference Manual, Rev. 2
10-14 Freescale Semiconductor
10.3.1.6 INTC Priority Select Registers (INTC_PSR0–329)
The INTC_PSR n allows you to select a priority for each interrupt request source (peripheral IRQs or
software-settable IRQs). Each priority select register (INTC_PSR n) is assigned to the IRQ source vector
with the same number. For example, the software-settable IRQs 0–7 are assigned vectors 0–7, and their
priorities are configured in INTC_PSR0–INTC_PSR7, respectively. The peripheral interrupt requests are
assigned vectors 8–329 and their priorities are configured in priority select registers INTC_PSR8 through
INTC_PSR329, respectively.
Although INTC_PSR n is 8 bits wide, you can use a single 16-bit or 32-bit access, provided that it does not
cross a 32-bit boundary.
NOTE
Do not modify the PRI
n
field in INTC_PSR
n
when the IRQ is asserted.
Table 10-7. INTC_SSCIR n Field Descriptions
Field Description
0–5 Reserved, must be cleared.
6
SET n
Set flag bits. Writing a 1 sets the corresponding CLR n bit. Writing a 0 has no effect. Each SET n is always read as a 0.
7
CLR n
Clear flag bits. CLR n is the flag bit. Writing a 1 to CLR n clears it provided that a 1 is not written simultaneously to its
corresponding SET n bit. Writing a 0 to CLR n has no effect.
0 Interrupt request not pending within INTC.
1 Interrupt request pending within INTC.
Address: Base + n (INTC_PSR n ); n = 0–329 Access: R/W
0 1 2 3 4 5 6 7
R 0 0 0 0
PRI n
W
Reset 0 0 0 0 0 0 0 0
Figure 10-13. INTC Priority Select Registers (INTC_PSR n )
Table 10-8. INTC_PSR n Field Descriptions
Field Description
0–3 Reserved, must be cleared.
4–7
PRI n
Priority select. Selects the priority for corresponding interrupt request.
1111 Priority 15 (highest)
1110 Priority 14
...
0001 Priority 1
0000 Priority 0 (lowest)