NXP Semiconductors MPC5566, Reference Manual

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Nexus
MPC5566 Microcontroller Reference Manual, Rev. 2
25-60 Freescale Semiconductor
• Upon data trace write/read after the previous DTM message was lost due to a collision entering the
FIFO between the DTM message and any of the following: watchpoint message, ownership trace
message, or branch trace message
Data trace synchronization messages provide the full address (without leading zeros) and insure that
development tools fully synchronize with data trace regularly. Synchronization messages provide a
reference address for subsequent data messages, in which only the unique portion of the data trace address
is transmitted. The format for data trace write/read with sync. messages is as follows:
Figure 25-46. Data Write/Read with Sync. Message Format
Exception conditions that result in data trace synchronization are summarized in Table 25-37 .
Table 25-37. Data Trace Exception Summary
Exception Condition Exception Handling
System Reset Negation At the negation of JTAG reset (JCOMP), queue pointers, counters, state machines,
and registers within the NZ6C3 module are reset. If data trace is enabled, the first
data trace message is a data write/read with sync. message.
Data Trace Enabled The first data trace message (after data trace has been enabled) is a
synchronization message.
Exit from Low Power/Debug Upon exiting from low power or debug modes, the next data trace message is
converted to a data write/read with sync. message.
Queue Overrun An error message occurs when a new message cannot be queued due to a full
message queue. The FIFO discards messages until it has completely emptied the
queue. After the queue is empty, an error message is queued that indicates the
message types denied queuing while the FIFO was emptying. The next DTM
message in the queue is a data write/read with sync. message.
Periodic Data Trace Sync. A forced synchronization occurs periodically after 255 data trace messages have
been queued. A data write/read with sync. message is queued. The periodic data
trace message counter then resets.
Event In If the Nexus module is enabled, a EVTI assertion initiates a data trace write/read
with sync. message upon the next data write/read (if data trace is enabled and the
EIC bits of the DC1 register have enabled this feature).
Attempted Access to Secure
Memory For devices which implement security, any attempted read or write to secure
memory locations temporarily disables data trace and loses the DTM. A
subsequent read/write queues a data trace read/write with sync. message.
Collision Priority All messages have the following priority: WPM
−>
OTM
−>
BTM
−>
DTM. A DTM
message which attempts to enter the queue at the same time as a watchpoint
message or ownership trace message or branch trace message can be lost. A
subsequent read/write queues a data trace read/write with sync. message.
DATA
MSB LSB
2 3 4
F-ADDR DSZ SRC
5
4 bits
1
TCODE (001101 or 001110)
3 bits 1 – 32 bits 1 – 64 bits 6 bits
Max length = 109 bits; Min length = 15 bits