NXP Semiconductors MPC5566, Reference Manual

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External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
12-26 Freescale Semiconductor
NOTE
Due to testing and complexity concerns, multi-master (or master/slave)
operation between an MPC55xx and MPC5xx is not guaranteed.
12.4.1.18 Misaligned Access Support
The EBI supports misaligned non-burst chip-select transfers only from internal masters. The EBI aligns
the accesses when it transmits data to the external bus (splitting them into multiple-aligned accesses) to
connect external devices that only support aligned accesses. Burst accesses (internal master) must be
32-bit aligned.
12.4.1.18.1 Misaligned Access Support (32-bit)
Table 12-14 shows the misaligned access cases supported by a 32-bit implementation, as detected on the
internal master bus. No support is available for all other misaligned access cases. If a misaligned access
occurs that is not supported (such as a non-chip-select or misaligned burst access), the EBI generates a
misaligned access error on the internal bus and does not start the access (nor assert TEA) externally.
Table 12-15 shows which external transfers are generated by the EBI for the misaligned access cases in
Table 12-14 , for each port size.
The number of external transfers for each internal AHB master request is determined by the HSIZE value
for that request relative to the port size. For example, a halfword write to 0
×000
3 (misaligned case #4) with
16-bit port size results in four external 16-bit transfers because of the transfer granularity of 32 bits. For
Table 12-14. Misalignment Cases Supported by a 32-bit Internal EBI
Case
Numbers
1
1
This is the misaligned case number. Only transfers where HUNALIGN = 1 are numbered as misaligned cases.
All other case numbers for byte misalignment do not apply to a 32-bit EBI implementation.
Program Size
and
Byte Offset
Address
[30:31]
2, 3
2
The address on internal master AHB bus is not necessarily the address on external ADDR pins.
3
The addresses with a ‘z’ increment an additional 32-bit word compared to the previous AHB access.
Data Bus Byte Strobes
4
4
Internal byte strobe signals.
Port Size
(HSIZE
5
)
5
Internal signal on the AHB bus: 00 = 8 bits; 01 = 16 bits; 10 = 32 bits. HSIZE uses the smallest aligned container that has all
the requested bytes, which can result in extra EBI external transfers.
Byte Alignment
(HUNALIGN)
External bus
big-endian
AHB bus
little-endian
1 Half-word @ 0x0001 01 0110 0110 10 = 32 bits 1 = Misaligned
4 Half-word @ 0x0003
(two AHB transfers) 11
z00
0001
1000 1000
0001 01 = 16 bits
6
00 = 8 bits
6
The EBI internally treats this case as if HSIZE = 00 (1-byte access).
1 = Misaligned
0 = Aligned
8 Word @ 0x0001
(two AHB transfers)
01
0111
1000 1110
0001 10 = 32 bits
00 = 8 bits 1 = Misaligned
0 = Aligned
9 Word @ 0x0002
(two AHB transfers)
10
0011
1100 1100
0011 10 = 32 bits
01 = 16 bits 1 = Misaligned
0 = Aligned
10
11 Word @ 0x0003
(two AHB transfers) 11
z00
0001
1110 1000
0111 10 = 32 bits
6
10 = 32 bits
1 = Misaligned
1 = Misaligned