NXP Semiconductors MPC5566, Reference Manual

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External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-73
Figure 12-50. Back-to-Back 32-bit Reads to CS, CAL_CS Banks
12.5 Initialization and Application Information
12.5.1 Booting from External Memory
The EBI block does not support booting directly to external memory (i.e. fetching the first instruction after
reset externally). The MCU uses an internal boot assist module, which executes after each reset. The BAM
code performs basic configuration of the EBI block, allowing for external boot if desired. See
16.1.3,
“Modes of Operation ,” for detail information about the boot modes supported by the MCU; booting is not
possible from external memory on the calibration bus.
If code in external memory must write EBI registers, avoid modifying EBI registers while external
accesses are in progress by using the following method:
1. Copy to internal SRAM the code that writes to the EBI registers (plus a return branch)
2. Branch to internal SRAM to run the code, ending with a branch back to external flash
12.5.2 Running with SDR (Single Data Rate) Burst Memories
This includes flash and external SRAM memories with a compatible burst interface. BDIP is required only
for some SDR memories.
Figure 12-48 shows a block diagram of an MCU connected to a 32-bit SDR burst
memory.
DATA is valid
CLKOUT
ADDR[8:31]
TS
DATA[0:31]
TA
RD_WR
TSIZ[0:1]
BDIP
OE
CAL_CS [ y ]
00
DATA is valid
CS [ n ]