NXP Semiconductors MPC5566, Reference Manual

Page: 642 / 1268

Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 15-33
15.4.3 Microcontroller Initialization
In the FEC, the descriptor control RISC initializes some registers after ECR[ETHER_EN] is asserted.
After the microcontroller initialization sequence is complete, the hardware is ready for operation.
Table 15-31 shows microcontroller initialization operations.
15.4.4 Application Initialization (After Asserting ECR[ETHER_EN])
After asserting ECR[ETHER_EN], the application can set up the buffer/frame descriptors and write to the
TDAR and RDAR. See
Section 15.5, “Buffer Descriptors ” for more details.
15.4.5 Network Interface Options
The FEC supports both an MII interface for 10/100 Mbps Ethernet and a 7-wire serial interface for 10
Mbps Ethernet. The interface mode is selected by the RCR[MII_MODE] bit. In MII mode
(RCR[MII_MODE] = 1), there are 18 signals defined by the IEEE
®
802.3 standard and supported by the
EMAC. These signals are shown in Table 15-32 below.
Initialize ETDSR
Initialize (Empty) Transmit Descriptor ring
Initialize (Empty) Receive Descriptor ring
Table 15-31. Microcontroller Initialization
Description
Initialize Backoff Random Number Seed
Activate Receiver
Activate Transmitter
Clear Transmit FIFO
Clear Receive FIFO
Initialize Transmit Ring Pointer
Initialize Receive Ring Pointer
Initialize FIFO Count Registers
Table 15-32. MII Mode
Signal Description EMAC Signal
Transmit Clock FEC_TX_CLK
Transmit Enable FEC_TX_EN
Transmit Data FEC_TXD[3:0]
Table 15-30. FEC Application Initialization (Before ECR[ETHER_EN]) (continued)
Description