NXP Semiconductors MPC5566, Reference Manual

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Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
17-76 Freescale Semiconductor
If the prescaler ratio is 9, the prescaled clock pulses every nine clock cycles and the internal counter
increments every nine clock cycles. The high pulse allows the EMIOS_CCNTR
n to increment as long as
no other conditions disable this counter. The match signal is generated by pulsing every time the internal
counter matches the programmed match value. For a programmed match value, the time base-period
becomes smaller as the prescaler ratio increases.
Figure 17-57 shows the prescaler ratio equal to 1, therefore the prescaled clock remains high and
continuously enables the internal counter (EMIOS_CCNTR n ):
Figure 17-57. eMIOS Time Base Generation Block Diagram
Figure 17-58 shows the prescaler ratio equal to one, therefore the prescaled clock remains high and
continuously enables the internal counter (EMIOS_CCNTR n ):
Figure 17-58. eMIOS Time Base Example — Fastest Prescaler Ratio = 1
Global prescaler
GPREN GPRE
System
Clock prescaler
UCPREN UCPRE
Ratio = (GPRE + 1)
×
(UCPRE + 1)
Prescaled clock
CCNTR n
internal counter
Match signal
Match value
clock
Prescaled clock
(Ratio = 1, bypassed)
Internal counter
1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3
Match value = 3
Initial time base period
the internal counter, starting another period.
Clock
EMIOS_CCNTR n
includes the match value.
Match occurs
0 1 2
1 2
3 0 1 2 3
1 2
3
1 2
3
1 2 3
The next clock cycle clears