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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-102
Freescale Semiconductor
<xrefblue>Figure 19-56. When a data transmission operation is performed, data in the transmit registers
is serially shifted twenty-six bit positions into the receive registers by the FCK clock from the master; data
is exchanged between the master and the slave. Data in the master transmit shift register in the beginning
of a transmission operation becomes the output data for the slave, and data in the master receive shift
register after a transmission operation is the input data from the slave.
Figure 19-56. Full Duplex Pin Connection
19.4.8.1
eQADC SSI Data Transmission Protocol
shows the timing of an eQADC SSI transmission operation. The main characteristics of this
protocol are the following:
•
FCK is free running, it does not stop between data transmissions. FCK is driven low:
— When the serial interface is disabled
— In stop/debug mode
— Immediately after reset
•
Frame size is fixed to 26 bits.
•
Msb bit is always transmitted first.
•
Master drives data on the positive edge of FCK and latches incoming data on the next positive edge
of FCK.
•
Slave drives data on the positive edge of FCK and latches incoming data on the negative edge of
FCK.
Master initiates a data transmission by driving SDS low, and its msb bit on SDO on the positive edge of
FCK. After an asserted SDS is detected, the slave shifts its data out, one bit at a time, on every FCK
positive edge. Both the master and the slave drive new data on the serial lines on every FCK positive edge.
This process continues until all the initial 26-bits in the master shift register are moved into the slave shift
register. t
DT
is the delay between two consecutive serial transmissions, time during which SDS is negated.
When ready to start of the next transmission, the slave must drive the msb bit of the message on every
positive edge of FCK regardless of the state of the SDS signal. On the next positive edge, the second bit
of the message is conditionally driven according to if an asserted SDS was detected by the slave on the
preceding FCK negative edge. This is an important requisite since the SDS and the FCK are not
Transmit shift register
Receive shift register
Data registers
Receive shift register
Transmit shift register
CFIFOs and RFIFOs
SDI
SDO
FCK
SDS
Baud rate
generator
Master
Slave
Summary of Contents for MPC5566
Page 81: ...Introduction MPC5566 Microcontroller Reference Manual Rev 2 1 24 Freescale Semiconductor...
Page 135: ...Signal Description MPC5566 Microcontroller Reference Manual Rev 2 2 54 Freescale Semiconductor...
Page 189: ...Reset MPC5566 Microcontroller Reference Manual Rev 2 4 20 Freescale Semiconductor...
Page 603: ...Flash Memory MPC5566 Microcontroller Reference Manual Rev 2 13 38 Freescale Semiconductor...
Page 609: ...SRAM MPC5566 Microcontroller Reference Manual Rev 2 14 6 Freescale Semiconductor...
Page 1073: ...MPC5566 Microcontroller Reference Manual Rev 2 22 36 Freescale Semiconductor...
Page 1185: ...Nexus MPC5566 Microcontroller Reference Manual Rev 2 25 92 Freescale Semiconductor...