NXP Semiconductors MPC5566, Reference Manual

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Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
15-36 Freescale Semiconductor
Once a collision window (64 bytes) of data has been received and if address recognition has not rejected
the frame, the receive FIFO is signalled that the frame is “accepted” and can be passed on to the DMA. If
the frame is a runt (due to collision) or is rejected by address recognition, the receive FIFO is notified to
“reject” the frame. Thus, no collision fragments are presented to the application except late collisions,
which indicate serious LAN problems.
During reception, the Ethernet controller checks for various error conditions and once the entire frame is
written into the FIFO, a 32-bit frame status word is written into the FIFO. This status word contains the
M, BC, MC, LG, NO, CR, OV and TR status bits, and the frame length. See
Section 15.4.14.2, “Reception
Errors ” for more details.
Receive buffer (RXB) and frame interrupts (RFINT) can be generated if enabled by the EIMR register. A
receive error interrupt is babbling receiver error (BABR). Receive frames are not truncated if they exceed
the max frame length (MAX_FL); however, the BABR interrupt occurs and the LG bit in the receive buffer
descriptor (RxBD) is set. See
Section 15.5.2, “Ethernet Receive Buffer Descriptor (RxBD) ” for more
details.
When the receive frame is complete, the FEC sets the L-bit in the RxBD, writes the other frame status bits
into the RxBD, and clears the E-bit. The Ethernet controller next generates a maskable interrupt (RFINT
bit in EIR, maskable by RFIEN bit in EIMR), indicating that a frame has been received and is in memory.
The Ethernet controller then waits for a new frame.
The Ethernet controller receives serial data LSB first.
15.4.8 Ethernet Address Recognition
The FEC filters the received frames based on the type of destination address (DA) — individual (unicast),
group (multicast), or broadcast (all-ones group address). The difference between an individual address and
a group address is determined by the I/G bit in the destination address field. A flowchart for address
recognition on received frames is illustrated in the figures below.
Address recognition is accomplished through the use of the receive block and microcode running on the
microcontroller. The flowchart shown in
Figure 15-28 illustrates the address recognition decisions made
by the receive block, while Figure 15-29 illustrates the decisions made by the microcontroller.
If the DA is a broadcast address and broadcast reject (RCR[BC_REJ]) is deasserted, then the frame is
accepted unconditionally, as shown in
Figure 15-28 . Otherwise, if the DA is not a broadcast address, then
the microcontroller runs the address recognition subroutine, as shown in Figure 15-29 .
If the DA is a group (multicast) address and flow control is disabled, then the microcontroller performs a
group hash table lookup using the 64-entry hash table programmed in GAUR and GALR. If a hash match
occurs, the receiver accepts the frame.
If flow control is enabled, the microcontroller does an exact address match check between the DA and the
designated PAUSE DA (01:80:C2:00:00:01). If the receive block determines that the received frame is a
valid PAUSE frame, then the frame is rejected. The receiver detects a PAUSE frame with the DA field set
to the designated PAUSE DA or the unicast physical address.
If the DA is the individual (unicast) address, the microcontroller performs an individual exact match
comparison between the DA and 48-bit physical address that the application programs in the PALR and