NXP Semiconductors MPC5566, Reference Manual

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Nexus
MPC5566 Microcontroller Reference Manual, Rev. 2
25-78 Freescale Semiconductor
25.17.2.2 Watchpoint Trigger Register (WT)
The watchpoint trigger register allows the watchpoints defined internally to the NXDM modules to trigger
actions. These watchpoints can control data trace enable and disable. The WT bits can be used to produce
an address related window for triggering trace messages.
NOTE
The WT bits ONLY enable data trace if the tm bits within the development
control register (DC) have not already been set to enable data trace.
25.17.2.3 Data Trace Control Register (DTC)
The data trace control register controls whether DTM Messages are restricted to reads, writes or both for
a user programmable address range. There are two data trace channels controlled by the DTC for the
NXDM module.
Access: R/W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0
DTS DTE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 25-57. Watchpoint Trigger Register (WT)
Table 25-49. WT Field Description
Field Description
31–26 Reserved, read as 0.
25–23
DTS
DTS - Data trace start control
000 Trigger disabled
001–100 Reserved
101 Use internal watchpoint #1 (BWA1 register)
110 Use internal watchpoint #2 (BWA2 register)
111 Reserved
22–20
DTE
DTE - Data trace end control
000 Trigger disabled
001–100 Reserved
101 Use internal watchpoint #1 (BWA1 register)
110 Use internal watchpoint #2 (BWA2 register)
111 Reserved
19–0 Reserved, read as 0.
Access: R/W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RWT1 RWT2
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RC1 RC2
0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 25-58. Data Trace Control Register (DTC)