NXP Semiconductors MPC5566, Reference Manual

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Addendum for Revision 2.0
MPC5566 Reference Manual Addendum, Rev. 2
Freescale Semiconductor 3
Figure 5-2, “Master Privilege
Control Registers”/Page 5-5
Change read status for bits 20–31 from zero to reserved.
Table A-1, “Module Base
Addresses”/Page A-1
Correct names of peripheral bridge modules by adding underscore (PBRIDGEA becomes
PBRIDGE_A
, PBRIDGEB becomes PBRIDGE_B). Only two rows of the table are changed.
Table A-2, “MPC5566 Detailed
Register Map”/Page A-2
Correct names of peripheral bridge A control registers by adding underscore (PBRIDGEA_ x
becomes PBRIDGE_A_ x ).
Table 1. MPC5566RM Rev 2.0 addendum
Location Description
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
MB
W4 MT
R4
MT
W4 MPL
4
W
Reset 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1
Access Field 4 Access Field 5 Access Field 6 Access Field 7
Module Base Address Page
Peripheral Bridge A (PBRIDGE_A) 0xC3F0_0000 Page A-2
Peripheral Bridge B (PBRIDGE_B) 0xFFF0_0000 Page A-35
Register Description Register Name
Used
Size
Address
Peripheral bridge A master privilege
control register PBRIDGE_A_MPCR 32-bit Base + 0x0000
Reserved — — Base +
(0x0004-0x001F)
Peripheral bridge A peripheral access
control register 0 PBRIDGE_A_PACR0 32-bit Base + 0x0020
Reserved — — Base +
(0x0024-0x003F)
Peripheral bridge A off-platform
peripheral access control register 0 PBRIDGE_A_OPACR0 32-bit Base + 0x0040
Peripheral bridge A off-platform
peripheral access control register 1 PBRIDGE_A_OPACR1 32-bit Base + 0x0044
Peripheral bridge A off-platform
peripheral access control register 2 PBRIDGE_A_OPACR2 32-bit Base + 0x0048
Reserved — — Base + (0x004C-
0xC3F7_FFFF)