NXP Semiconductors MPC5566, Reference Manual

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External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-57
master does a transaction to internal address space, the EBI only drives TA for the cycle it asserts TA to
return data and for one cycle afterwards to ensure fast negation.
If no device responds by asserting TA within the programmed timeout period (BMT in EBI_BMCR) after
the EBI initiates the bus cycle, the internal bus monitor (if enabled) asserts TEA to terminate the cycle. An
external device also drive TEA when it detects an error on an external transaction. TEA assertion causes
the cycle to terminate and the processor to enter exception processing for the error condition. To properly
control termination of a bus cycle for a bus error with external circuitry, TEA must be asserted at the same
time or before (external) TA is asserted. TEA must be negated before the second rising edge after it was
sampled asserted to avoid the detection of an error for the following bus cycle initiated. TEA is only driven
by the EBI during the cycle where the EBI is asserting TEA and the cycle immediately following this
assertion (for fast negation). During all other cycles, the EBI relies on a weak internal pullup to hold TEA
negated. This allows an external device to assert TEA when it needs to indicate an error. External devices
must follow the same protocol as the EBI, only driving TEA during the assertion cycle and one cycle
afterwards for negation.
NOTE
When an external master asserts TEA to timeout a transaction to an internal
address on the MCU, the EBI cannot terminate the transfer internally.
Therefore, subsequent TS assertions by the external master are not serviced
by the EBI until the original transfer is complete internally and the EBI
returns to an idle state. The internal slaves must respond with either valid
data or an error indication within a reasonable period of time to avoid
hanging the system.
When TEA is asserted from an external source, the EBI uses a latched version of TEA (one cycle delayed)
to help make timing at high frequencies. This means that for any accesses where the EBI drives TA (chip
select accesses and external master accesses to EBI), a TEA assertion that occurs one cycle before or
during the last TA of the access is not needed by the EBI, since it completes the access internally before it
detects the latched TEA assertion. This means that non-burst chip select accesses with no wait states (SCY
equal to zero) cannot be reliably terminated by external TEA. If external error termination is required for
such a device, the EBI must configure SCY greater than or equal to one.
NOTE
In some access cases that use a chip select and internally-driven TA, a TEA
that occurs one cycle before or during the TA cycle, or when SCY equals
zero, the cycle can terminate with an incorrect error. Because correct error
termination is not guaranteed, always assert TEA at least two cycles before
an internally-driven TA cycle for the error to terminate correctly.
External TEA assertion that occurs during the same cycle that TS is asserted by the EBI is always treated
as an error (terminating the access) regardless of SCY.