NXP Semiconductors MPC5566, Reference Manual

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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-68 Freescale Semiconductor
NOTE
If MODE n is not disabled, it must not be changed to any other mode besides
disabled. If MODE n is disabled and the CFIFO status is IDLE, MODE n can
be changed to any other mode.
If MODE n is changed to disabled:
• The CFIFO execution status changes to IDLE. The timing of this change depends on whether a
command is being transferred or not:
— When no command transfer is in progress, the eQADC switches the CFIFO to IDLE status
immediately.
— When a command transfer to an on-chip ADC is in progress, the eQADC completes the
transfer, updates TC_CF, and switches CFIFO status to IDLE. Command transfers to the
internal ADCs are considered completed when a command is written to the relevant buffer.
— When a command transfer to an external command buffer is in progress, the eQADC aborts the
transfer and switches CFIFO status to IDLE. If the eQADC cannot abort the transfer, that is
when the 26th bit of the serial message has being already shifted out, the eQADC completes
the transfer, updates TC_CF and then switches CFIFO status to IDLE.
• The CFIFOs are not invalidated automatically. The CFIFO still can be invalidated by writing a 1
to the CFINV
n bit (see Section 19.3.2.6, “eQADC CFIFO Control Registers 0–5
(EQADC_CFCRn) ”). Certify that CFS has changed to IDLE before setting CFINV n .
• The TC_CF n value also is not reset automatically, but it can be reset by writing 0 to it.
• The EQADC_FISRn[SSS] bit (see Section 19.3.2.8, “eQADC FIFO and Interrupt Status Registers
0–5 (EQADC_FISRn) ”) is negated. The SSS bit can be set even if a 1 is written to the
EQADC_CFCR[SSE] bit (see Section 19.3.2.6, “eQADC CFIFO Control Registers 0–5
(EQADC_CFCRn) ”) in the same write that the MODE n field is changed to a value other than
disabled.
• The trigger detection hardware is reset. If MODE n is changed from disabled to an edge trigger
mode, a new edge, matching that edge trigger mode, is needed to trigger the command transfers
from the CFIFO.
NOTE
CFIFO fill requests, generated when the CFFF asserts, are not automatically
halted when MODE
n is changed to disabled. CFIFO fill requests are still
generated until EQADC_IDCRn[CFFE] bit is cleared. Refer to Section
Section 19.3.2.7, “eQADC Interrupt and eDMA Control Registers 0–5
(EQADC_IDCRn)
.”
19.4.3.5.2 Single-Scan Mode
In single-scan mode, a single pass through a sequence of command messages in the user-defined command
queue is performed.
In single-scan software trigger mode, the CFIFO is triggered by an asserted single-scan status bit,
EQADC_FISRn[SSS] (see
Section 19.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5