NXP Semiconductors MPC5566, Reference Manual

Page: 1082 / 1268

MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 24-1
Chapter 24
IEEE 1149.1 Test Access Port Controller (JTAGC)
24.1 Introduction
The JTAG port of the device consists of four inputs and one output. These pins include JTAG compliance
select (JCOMP), test data input (TDI), test data output (TDO), test mode select (TMS), and test clock input
(TCK). TDI, TDO, TMS, and TCK are compliant with the IEEE 1149.1-2001 standard and are shared with
the NDI through the test access port (TAP) interface.
24.1.1 Block Diagram
Figure 24-1 is a block diagram of the JTAG Controller (JTAGC).
Figure 24-1. JTAG Controller Block Diagram
TCK
TMS
TDI
Test access port (TAP)
TDO
32-bit device identification register
Boundary scan register
.
.
controller
1-bit bypass register
.
5-bit TAP instruction decoder
5-bit TAP instruction register
.
.
.
JCOMP
Power-on
reset