NXP Semiconductors MPC5566, Reference Manual

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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-52 Freescale Semiconductor
Table 19-36. On-Chip ADC Field Descriptions: Read Configuration
Field Description
0
EOQ
End-of-queue. Asserted in the last command of a command queue to indicate to the eQADC that a scan of the
queue is completed. EOQ instructs the eQADC to reset its current CFIFO transfer counter value (TC_CF) to 0.
Depending on the CFIFO mode of operation, the CFIFO status changes upon the detection of an asserted EOQ
bit on the last transferred command. Refer to
Section 19.4.3.5, “CFIFO Scan Trigger Modes ,” for details.
0 Not the last entry of the command queue.
1 Last entry of the command queue.
Note: If both the pause and EOQ bits are asserted in the same command message the respective flags are set,
but the CFIFO status changes as if only the EOQ bit were asserted.
1
PAUSE
Pause bit. Allows software to create sub-queues within a command queue. When the eQADC completes the
transfer of a command with an asserted pause bit, the CFIFO enters the WAITING FOR TRIGGER state. Refer
to
Section 19.4.3.6.1, “CFIFO Operation Status ,” for a description of the state transitions. The pause bit is only
valid when CFIFO operation mode is configured to single or continuous-scan edge trigger mode.
0 Do not enter WAITING FOR TRIGGER state after transfer of the current command message.
1 Enter WAITING FOR TRIGGER state after transfer of the current command message.
Note: If both the pause and EOQ bits are asserted in the same command message the respective flags are set,
but the CFIFO status changes as if only the EOQ bit were asserted.
2–4 Reserved.
5
EB
External buffer bit. Always clear this bit for messages sent to an on-chip ADC.
0 Command is sent to an internal command buffer.
1 Command is sent to an external command buffer.
6
BN
Buffer number. Indicates to which buffer the message is sent. Buffers 1 and 0 can either be internal or external
depending on the EBI bit setting.
0 Message buffer 0.
1 Message buffer 1.
7
R/W
Read/write. An asserted R/W bit indicates a read configuration command.
0 Write
1 Read