NXP Semiconductors MPC5566, Reference Manual

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External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
12-52 Freescale Semiconductor
Figure 12-33. Central Arbitration Timing Diagram
12.4.2.8.2 Internal Bus Arbiter
When an MCU is configured to use the internal bus arbiter, that MCU is parked on the bus. The parking
feature allows the MCU to skip the bus request phase, and if BB is negated, assert BB, and initiate the
transaction without waiting for bus grant from the arbiter. The priority between internal and external
masters over the external bus is determined by the EARP field of the EBI_MCR. See
Table 12-7 for the
EARP field description.
By default, internal and external masters are treated with equal priority, with each having to relinquish the
bus after the current transaction if another master is requesting it. If internal and external requests for the
bus occur in the same cycle, the internal arbiter grants the bus to the master who least recently used the
bus. If no other master is requesting the bus, the bus continues to be granted to the current master, and the
current master start another access without re-arbitrating for the bus.
If the priority field is configured for unequal priority between internal and external masters, then whenever
requests are pending from both masters, the one with higher priority is always granted the bus. However,
in all cases, a transaction in progress (or that has already been granted, for example MCU bus wait and
external bus wait states) is allowed to complete, even when a request from a higher priority master is
pending.
There is a minimum of one cycle between the positive edge CLKOUT that a BR assertion is sampled by
the EBI and the positive edge CLKOUT where BG is driven out asserted by the EBI. This is to prevent
timing problems that can limit the operating frequency in external master mode.
M0 receives bus grant and bus busy negated for second cycle
Both masters configured for external arbitration
CLKOUT
BR[0]
BB
ADDR + ATTR
1
CS[ n ]
BG[0]
BR[1]
BG[1]
TA
TS
M1 receives bus grant
and bus busy negated
for second cycle
Both
masters
off
Master 0
negates BB and
‘turns off’
(three-states controls)
Master 1
asserts BB and
‘turns on’
(drives controls)
Master 0
asserts BB and
‘turns on’
(drives controls)
1
ATTR refers to control signals such as RD_WR and TSIZ.