MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
22-25
22.4.2
Transmit Process
The CPU prepares a message buffer for transmission by executing the following steps:
•
Write the CODE field of the control and status word to keep the TX MB inactive (code = 1000).
•
Write the ID word.
•
Write the DATA bytes.
•
Write the LENGTH, SRR, IDE, RTR, and CODE fields of the control and status word to activate
the TX MB.
The first and last steps are mandatory.
22.4.2.1
Arbitration Process
This process selects the next MB to transmit. All MBs programmed as transmit buffers are scanned to find
the lowest ID
1
or the lowest MB number, depending on the LBUF bit in the CAN
x
_CR. The selected MB
is transferred to an internal serial message buffer (SMB), which is not software accessible, and then
transmitted.
The arbitration process is triggered by the following events:
•
During the CRC field of the CAN frame
•
During the error delimiter field of the CAN frame
•
During Intermission, if the winner MB defined in a previous arbitration was deactivated, or if there
was no MB to transmit, but the CPU wrote to the C/S word of any MB after the previous arbitration
finished.
•
When MBM is in idle or bus off state and the CPU writes to the C/S word of any MB
•
Upon leaving freeze mode
When arbitration is complete, and an MB is selected to transmit, the frame is first transferred to the SMB.
This is called ‘move out.’ After move out, the CAN transmit machine starts to transmit the frame according
to the CAN protocol rules. FlexCAN2 transmits up to eight data bytes, even if the value of the data length
code (DLC) is greater.
At the end of a successful transmission, the value of the free running timer at the beginning of the identifier
field is written into the TIME STAMP field in the MB, the CODE field in the control and status word of
the MB is updated, a status flag is set in CAN
x
_IFRL or CAN
x
_IFRH, and an MB interrupt is generated
if allowed by the corresponding interrupt mask register bit.
1. Actually, if LBUF is negated, the arbitration considers not only the ID, but also the RTR and IDE bits placed inside the ID at the
same positions they are transmitted in the CAN frame.
Summary of Contents for MPC5566
Page 81: ...Introduction MPC5566 Microcontroller Reference Manual Rev 2 1 24 Freescale Semiconductor...
Page 135: ...Signal Description MPC5566 Microcontroller Reference Manual Rev 2 2 54 Freescale Semiconductor...
Page 189: ...Reset MPC5566 Microcontroller Reference Manual Rev 2 4 20 Freescale Semiconductor...
Page 603: ...Flash Memory MPC5566 Microcontroller Reference Manual Rev 2 13 38 Freescale Semiconductor...
Page 609: ...SRAM MPC5566 Microcontroller Reference Manual Rev 2 14 6 Freescale Semiconductor...
Page 1073: ...MPC5566 Microcontroller Reference Manual Rev 2 22 36 Freescale Semiconductor...
Page 1185: ...Nexus MPC5566 Microcontroller Reference Manual Rev 2 25 92 Freescale Semiconductor...
