NXP Semiconductors MPC5566, Reference Manual

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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-38 Freescale Semiconductor
4
ADC n _
EMUX
ADC n external multiplexer enable. When ADC n _EMUX is asserted, the MA pins output digital values to the external
channel number selected to convert external multiplexer inputs. Refer to Section 19.4.6, “Internal/External
Multiplexing ,” for a detailed description about how ADC n _EMUX affects channel number decoding.
0 External multiplexer disabled; no external multiplexer channels can be selected.
1 External multiplexer enabled; external multiplexer channels can be selected.
Note: Both ADC n _EMUX bits must not be asserted at the same time.
Note: The ADC n _EMUX bit must only be written when the ADC n _EN bit is negated. ADC n _EMUX can be set during
the same write cycle used to set ADC n _EN.
5–10 Reserved.
11–15
ADC n _
CLK_PS
[0:4]
ADC n clock prescaler. The ADC n _CLK_PS field controls the system clock divide factor for the ADC n clock as in
Table 19-28 . Refer to Section 19.4.5.2, “ADC Clock and Conversion Speed ,” for details about how to set
ADC0/1_CLK_PS.
The ADC
n _CLK_PS field must only be written when the ADC n _EN bit is negated. This field can be configured during
the same write cycle used to set ADC n _EN.
Table 19-28. System Clock Divide Factor for ADC Clock
ADC n _CLK_PS[0:4]
System Clock
Divide Factor
0b00000 2
0b00001 4
0b00010 6
0b00011 8
0b00100 10
0b00101 12
0b00110 14
0b00111 16
0b01000 18
0b01001 20
0b01010 22
0b01011 24
0b01100 26
0b01101 28
0b01110 30
0b01111 32
0b10000 34
0b10001 36
0b10010 38
Table 19-27. ADC n _CR Field Descriptions (continued)
Field Description