NXP Semiconductors MPC5566, Reference Manual

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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 19-83
message from the on-chip ADCs or from the external device. The RFIFO counter logic counts the number
of entries in RFIFO and generates interrupt or eDMA requests to drain the RFIFO.
EQADC_FISRn[POPNXTPTR] (see Section 19.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5
(EQADC_FISRn) ”) indicates which entry is currently being addressed by the pop next data pointer, and
EQADC_FISRn[RFCTR] provides the number of entries stored in the RFIFO. Using POPNXTPTR and
RFCTR, the absolute addresses for pop next data pointer and receive next data pointer can be calculated
using the following formulas:
Pop Next Data Pointer Address= RFIFO n _BASE_A POPNXTPTR n x 4
Receive Next Data Pointer Address = RFIFO n _BASE_A
[(POPNXTPTR n + RFCTR n ) mod RFIFO_DEPTH] x 4
where
• a mod b returns the remainder of the division of a by b .
• RFIFO n _BASE_ADDRESS is the smallest memory mapped address allocated to an RFIFO n
entry.
• RFIFO_DEPTH is the number of entries contained in a RFIFO - four in this implementation.
When a new message arrives and RFIFO n is not full, the eQADC copies its contents into the entry pointed
by receive next data pointer. The RFIFO counter EQADC_FISR n [RFCTR n ] (see Section 19.3.2.8,
“eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn) ”) is incremented by 1, and the receive
next data pointer n is also incremented by 1 (or wrapped around) to point to the next empty entry in
RFIFO n . However, if the RFIFO n is full, the eQADC sets the EQADC_FISR n [RFOF] (see
Section 19.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn) ”). The RFIFO n
does not overwrite the older data in the RFIFO, the new data is ignored, and the receive next data pointer
n is not incremented or wrapped around. RFIFO n is full when the receive next data pointer n equals the
pop next data pointer n and RFCTR n is not 0. RFIFO n is empty when the receive next data pointer n equals
the pop next data pointer n and RFCTR n is 0.
When the eQADC RFIFO pop register n is read and the RFIFO n is not empty, the RFIFO counter RFCTR n
is decremented by 1, and the pop next data pointer is incremented by 1 (or wrapped around) to point to the
next RFIFO entry.
When the eQADC RFIFO pop register n is read and RFIFO n is empty, eQADC does not decrement the
counter value and the pop next data pointer n is not updated. The read value is undefined.