NXP Semiconductors MPC5566, Reference Manual

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Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 15-25
15.3.4.2.15 Descriptor Individual Lower Address (IALR)
The IALR register is written by the application. This register contains the lower 32 bits of the 64-bit
individual address hash table used in the address recognition process to check for possible match with the
DA field of receive frames with an individual DA. This register is not reset and must be initialized by the
application.
Address: Base + 0x0118 Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
IADDR1
W
Reset U
1
U U U U U U U U U U U U U U U
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
IADDR1
W
Reset U U U U U U U U U U U U U U U U
1
“U” signifies a bit that is uninitialized. See the Preface of the book.
Figure 15-18. Descriptor Individual Upper Address Register (IAUR)
Table 15-18. IAUR Field Descriptions
Field Descriptions
0–31
IADDR1
The upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames
with a unicast address. Bit 31 of IADDR1 contains hash index bit 63. Bit 0 of IADDR1 contains hash
index bit 32.
Address: Base + 0x011C Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
IADDR2
W
Reset U
1
U U U U U U U U U U U U U U U
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
IADDR2
W
Reset U U U U U U U U U U U U U U U U
1
“U” signifies a bit that is uninitialized. See the Preface of the book.
Figure 15-19. Descriptor Individual Lower Address Register (IALR)