NXP Semiconductors MPC5566, Reference Manual

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MPC5566 Microcontroller Reference Manual, Rev. 2
22-28 Freescale Semiconductor
process. However, deactivation is not permanent. The MB that was deactivated during the current
match/arbitration pass is available to transmit or receive in the next pass.
The purpose of deactivation is data coherency. The match/arbitration process scans the MBs to decide
which MB to transmit or receive. If the CPU updates the MB in the middle of a match or arbitration
process, the data coherency in the MB can become corrupt, therefore that MB is deactivated.
Match and arbitration are one-pass processes. After scanning all MBs, a winner is determined. If MBs are
changed after they are scanned, no re-evaluation is done to determine a new match/winner; and a frame
can be lost if the matched MB has been deactivated. If two RX MBs have a matching ID to a received
frame, then it is not guaranteed reception if the matching MB is deactivated after FlexCAN2 has scanned
the second.
22.4.4.1 Notes on TX Message Buffer Deactivation
There is a point in time until which the deactivation of a TX MB causes it not to be transmitted (end of
move out). After this point, it is transmitted but no interrupt is issued and the CODE field is not updated.
If a TX MB containing the lowest ID (or lowest buffer if LBUF is set) is deactivated after FlexCAN2 has
scanned it while in arbitration process, then FlexCAN2 can transmit a MB with an ID that is not the lowest
at that time.
22.4.4.2 Notes on RX Message Buffer Deactivation
If the deactivation occurs during move in, the move operation is aborted and no interrupt is issued, but the
MB contains mixed data from two different frames.
In case the CPU writes data into RX MB data words while it is being moved in, the move operation is
aborted and no interrupt is issued, but the control/status word can change to reflect FULL or OVRN. This
action must be avoided.
22.4.4.3 Data Coherency Mechanisms
The FlexCAN2 module has a mechanism to assure data coherency in both receive and transmit processes.
The mechanism includes a lock status for MBs and two internal storage areas, called serial message buffers
(SMB), to buffer frame transfers within FlexCAN. The details of the mechanism are the following:
• CPU reads the control and status word of an MB, which triggers a lock for that MB; therefore a
new RX frame that matches the MB cannot be written to the MB.
• To release a locked MB, the CPU must either lock another MB (by reading its control and status
word), or globally release any locked MB (by reading the free-running timer).
• If the CPU reads a RX MB while it is being transferred to (from) SMB, then the BUSY bit is set
in the CODE field of the control and status word. To ensure data coherency, the CPU must wait
until this BUSY bit is negated before further reading from that MB. In this case, the MB is not
locked.
• If the CPU deactivates a locked RX MB, then its lock status is negated, but no data is transferred
to the MB.