NXP Semiconductors MPC5566, Reference Manual

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Enhanced Direct Memory Access (eDMA)
MPC5566 Microcontroller Reference Manual, Rev. 2
9-30 Freescale Semiconductor
240–241
0x1C
[16:17]
BWC
[0:1]
Bandwidth control. This two-bit field provides a mechanism to effectively throttle the
amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes
the inner minor loop, it continuously generates read/write sequences until the minor count
is exhausted. This field forces the eDMA to stall after the completion of each read/write
access to control the bus request bandwidth seen by the system bus crossbar switch
(XBAR).
To minimize start-up latency, bandwidth control stalls are suppressed for the first two
system bus cycles and after the last write of each minor loop.
00 No eDMA engine stalls
01 Reserved
10 eDMA engine stalls for four cycles after each r/w
11 eDMA engine stalls for eight cycles after each r/w
242–247
0x1C
[18:23]
MAJOR.LINKCH
[0:5]
Link channel number. If channel-to-channel linking on major loop complete is disabled
(TCD.MAJOR.E_LINK = 0) then:
• No channel-to-channel linking (or chaining) is performed after the outer major loop
counter is exhausted.
Otherwise
• After the major loop counter is exhausted, the eDMA engine initiates a channel service
request at the channel defined by MAJOR.LINKCH[0:5] by setting that channel’s
TCD.START bit.
248
0x1C
[24]
DONE Channel done. This flag indicates the eDMA has completed the outer major loop. It is set
by the eDMA engine as the CITER count reaches zero; it is cleared by software or
hardware when the channel is activated (when the channel has begun to be processed
by the eDMA engine, not when the first data transfer occurs).
Note: This bit must be cleared to write the MAJOR.E_LINK or E_SG bits.
249
0x1C
[25]
ACTIVE Channel active. This flag signals the channel is currently in execution. It is set when
channel service begins, and is cleared by the eDMA engine as the inner minor loop
completes or if any error condition is detected.
250
0x1C
[26]
MAJOR.E_LINK Enable channel-to-channel linking on major loop completion. As the channel completes
the outer major loop, this flag enables the linking to another channel, defined by
MAJOR.LINKCH[0:5]. The link target channel initiates a channel service request via an
internal mechanism that sets the TCD.START bit of the specified channel.
NOTE: To support the dynamic linking coherency model, this field is forced to zero when
written to while the TCD.DONE bit is set.
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.
251
0x1C
[27]
E_SG Enable scatter/gather processing. As the channel completes the outer major loop, this
flag enables scatter/gather processing in the current channel. If enabled, the eDMA
engine uses DLAST_SGA as a memory pointer to a 0-modulo-32 address containing a
32-byte data structure which is loaded as the transfer control descriptor into the local
memory.
NOTE: To support the dynamic scatter/gather coherency model, this field is forced to zero
when written to while the TCD.DONE bit is set.
0 The current channel’s TCD is “normal” format.
1 The current channel’s TCD specifies a scatter gather format. The DLAST_SGA field
provides a memory pointer to the next TCD to be loaded into this channel after the
outer major loop completes its execution.
Table 9-19. TCD n Field Descriptions (continued)
Bits
Word Offset
[n:n]
Field Name Description