NXP Semiconductors MPC5566, Reference Manual

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MPC5566 Reference Manual Addendum, Rev. 2
Addendum for Revision 2.0
Freescale Semiconductor 6
Figure 11-9, “Synthesizer
Status Register
(FMPLL_SYNSR)”/Page
11-16
Correct the figure to reflect bits 23:28 and bits 30:31 as read-only.
Section 10.3.1.3, “INTC
Interrupt Acknowledge
Register
(INTC_IACKR)”/Page 10-12
Remove the first paragraph from the “Note”:
“The INTC_IACKR must not be read speculatively while in software vector mode. Therefore, for
future compatibility, the TLB entry covering the INTC_IACKR must be configured to be guarded.”
Table 10-3. INTC Memory
Map/Page 10-9
Add the following note at the end of this table:
Note:
To ensure compatibility with all PowerPC processors, the TLB entry covering the INTC memory
map must be configured as guarded, both in software and hardware vector modes.
• In software vector mode, the INTC_IACKR must not be read speculatively.
• In hardware vector mode, guarded writes to the INTC_CPR or INTC_EOIR complete before
the interrupt acknowledge signal from the processor asserts.
Table 10-9. MPC5566
Interrupt Request Sources/
Page 10-28
Update the note at the end of this table as follows:
Note:
The INTC has no spurious vector support. Therefore, if an asserted peripheral or software
settable interrupt request (whose PRI value in INTC_PSRn is higher than the PRI value in
INTC_CPR) negates before the interrupt request to the processor for that peripheral or software
settable interrupt request is acknowledged, the interrupt request to the processor still can assert
or remain asserted for that peripheral or software settable interrupt request. If the interrupt
request to the processor does assert or does remain asserted:
• The interrupt vector will correspond to that peripheral or software settable interrupt request.
• The PRI value in the INTC_CPR will be updated with the corresponding PRI value in
INTC_PSRn.
Furthermore, clearing the peripheral interrupt request's enable bit in the peripheral or,
alternatively, setting its mask bit has the same consequences as clearing its flag bit.Setting its
enable bit or clearing its mask bit while its flag bit is asserted has the same effect on the INTC
as an interrupt event setting the flag bit.
Table 1. MPC5566RM Rev 2.0 addendum
Location Description
Address: Base + 0x0004 Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0 0 0 0 0 0 LOLF LOC
MO
DE
PLL
SEL
PLL
REF
LOC
KS
LOC
K
LOC
F
CAL
DO
NE
CAL
PAS
S
W w1c w1c
Reset 0 0 0 0 0 0 0 0 —
1
—
1
—
1
—
1
—
2
0 0 0
1
Reset state determined during reset configuration.
2
Reset state determined during reset.
Note: “w1c” signifies that this bit is cleared by writing a 1 to it.
Synthesizer Status Register (FMPLL_SYNSR)