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NXP Semiconductors MPC5566, Reference Manual

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MPC5566 Microcontroller Reference Manual, Rev. 2

Freescale Semiconductor

22-21

 

18

ACKERR

Acknowledge error. Indicates that an acknowledge error has been detected by the transmitter node; that 
is, a dominant bit has not been detected during the ACK SLOT. A read clears ACKERR. 
0 No such occurrence
1 An ACK error occurred since last read of this register

19

CRCERR

Cyclic redundancy code error. Indicates that a CRC error has been detected by the receiver node; that is, 
the calculated CRC is different from the received. A read clears CRCERR. 
0 No such occurrence
1 A CRC error occurred since last read of this register.

20

FRMERR

Form error. Indicates that a form error has been detected by the receiver node; that is, a fixed-form bit field 
contains at least one illegal bit. A read clears FRMERR. 
0 No such occurrence
1 A form error occurred since last read of this register

21

STFERR

Stuffing error. Indicates that a stuffing error has been detected. A read clears STFERR. 
0 No such occurrence.
1 A stuffing error occurred since last read of this register.

22

TXWRN

TX error counter. This status bit indicates that repetitive errors are occurring during message transmission.
0 No such occurrence
1 TXECTR 

≥

 96

23

RXWRN

RX error counter. This status bit indicates when repetitive errors are occurring during messages reception.
0 No such occurrence
1 RXECTR 

≥ 

96

24

IDLE

CAN bus IDLE state. This status bit indicates when CAN bus is in IDLE state.
0 No such occurrence
1 CAN  bus  is  now  IDLE

25

TXRX

Current FlexCAN2 status (transmitting/receiving). This status bit indicates if FlexCAN2 is transmitting or 
receiving a message when the CAN bus is not in IDLE state. This bit has no meaning when IDLE is 
asserted.
0 FlexCAN2 is receiving a message (IDLE = 0)
1 FlexCAN2 is transmitting a message (IDLE = 0)

26–27

FLTCONF[0:1]

Fault confinement state. This status bit indicates the confinement state of the FlexCAN2 module. If the 
LOM bit in the CAN

x

_CR asserts, the FLTCONF field indicates “Error Passive”. Since the CAN

x

_CR is not 

affected by a soft reset, the FLTCONF field is not affected by a soft reset if the LOM bit asserts.
00 Error active
01 Error passive
1X Bus off

28

Reserved.

29

BOFFINT

Bus off interrupt. This status bit is set when FlexCAN2 is in the bus off state. If CAN

x

_CR[BOFFMSK] is 

set, an interrupt is generated to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
0 No such occurrence
1 FlexCAN2 module is in ‘Bus Off’ state

Table 22-12. CAN

x

_ESR Field Descriptions (continued)

Field

Description

Summary of Contents for MPC5566

Page 1: ...rved Freescale Semiconductor MPC5566RM Rev 2 1 05 2012 This MPC5566 Reference Manual set consists of the following files MPC5566 Reference Manual Addendum Rev 2 MPC5566 Microcontroller Reference Manua...

Page 2: ...the MPC5566 Microcontroller Reference Manual order number MPC5566RM For convenience the addenda items are grouped by revision Please check our website at http www freescale com powerarchitecture for...

Page 3: ...nly the Transmit Data Register Empty and LIN Transmit Data Ready flags drive the DMA request The Transmit Complete flag is not used Transfer Size TSIZ 0 1 Address 32 Bit Port Size 16 Bit Port Size1 NO...

Page 4: ...W4 MPL 4 W Reset 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 Access Field 4 Access Field 5 Access Field 6 Access Field 7 Module Base Address Page Peripheral Bridge A PBRIDGE_A 0xC3F0_0000 Page A 2 Peripheral Bri...

Page 5: ...al bridge B peripheral access control register 0 PBRIDGE_B_PACR0 32 bit Base 0x0020 Reserved Base 0x0024 0x0027 Peripheral bridge B peripheral access control register 2 PBRIDGE_B_PACR2 32 bit Base 0x0...

Page 6: ...the EDMA_IRQRH and EDMA_IRQRL Section 8 3 Initialization and Application Information Page 8 15 Change the sentence There are eight ECC check bits for each 64 bit data doubleword to the following SRAM...

Page 7: ...an the PRI value in INTC_CPR negates before the interrupt request to the processor for that peripheral or software settable interrupt request is acknowledged the interrupt request to the processor sti...

Page 8: ...ruction after the GetResource system service executes all pending transactions have completed These pending transactions can include an ISR for a peripheral or software settable interrupt request whos...

Page 9: ...escription A Peripheral interrupt request 200 asserts during execution of ISR108 running at priority 1 B Interrupt request to processor asserts INTVEC in INTC_IACKR updates with vector for that periph...

Page 10: ...ular Input Output Subsystem eMIOS Clarified the description in Section 9 4 1 eDMA Microarchitecture Clarified the description in Section 9 3 1 13 eDMA Interrupt Request Registers EDMA_IRQRL Clarified...

Page 11: ...se nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation c...

Page 12: ...MPC5566 Microcontroller Reference Manual Devices Supported MPC5566 MPC5566 RM Rev 2 0 23 Apr 2008...

Page 13: ...such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims cost...

Page 14: ...nput Output System eMIOS 1 17 1 5 14 Enhanced Time Processing Unit eTPU 1 17 1 5 15 Enhanced Queued A D Converter eQADC 1 17 1 5 16 Deserial Serial Peripheral Interface DSPI 1 17 1 5 17 Enhanced Seria...

Page 15: ...Master Address Expansion GPIO ADDR 30 31 _ADDR 6 7 _GPIO 26 27 2 21 2 3 2 6 External Data GPIO DATA 0 15 _GPIO 28 43 2 21 2 3 2 7 External Data Ethernet Transmit Clock GPIO DATA 16 _FEC_TX_CLK_GPIO 4...

Page 16: ...In Progress GPIO BDIP_GPIO 63 2 23 2 3 2 26 External Write Byte Enable GPIO WE BE 0 3 _GPIO 64 67 2 23 2 3 2 27 External Output Enable GPIO OE_GPIO 68 2 23 2 3 2 28 External Transfer Start GPIO TS_GP...

Page 17: ...Receive eSCI A Receive GPIO CNRXA_RXDA_GPIO 84 2 26 2 3 5 3 FlexCAN B Transmit DSPI C GPIO CNTXB_PCSC 3 _GPIO 85 2 26 2 3 5 4 FlexCAN B Receive DSPI C GPIO CNRXB_PCSC 4 _GPIO 86 2 26 2 3 5 5 FlexCAN C...

Page 18: ...PI C GPIO SOUTB_PCSC 5 _GPIO 104 2 29 2 3 7 13 DSPI B DSPI D GPIO PCSB 0 _PCSD 2 _GPIO 105 2 29 2 3 7 14 DSPI B DSPI D GPIO PCSB 1 _PCSD 0 _GPIO 106 2 29 2 3 7 15 DSPI B DSPI C Data Output GPIO PCSB 2...

Page 19: ...DC Free Running Clock AN 15 _FCK 2 32 2 3 8 17 Analog Input AN 16 39 2 33 2 3 8 18 External Trigger GPIO ETRIG 0 1 _GPIO 111 112 2 33 2 3 8 19 Voltage Reference High VRH 2 33 2 3 8 20 Voltage Referenc...

Page 20: ...el DSPI B GPIO ETPUA 15 _PCSB 5 _GPIO 129 2 36 2 3 9 18 eTPU A Channel DSPI D GPIO ETPUA 16 _PCSD 1 _GPIO 130 2 36 2 3 9 19 eTPU A Channel DSPI D GPIO ETPUA 17 _PCSD 2 _GPIO 131 2 36 2 3 9 20 eTPU A C...

Page 21: ...Interrupt Request FlexCAN Transmit Data GPIO EMIOS 14 _IRQ 0 _CNTXD_GPIO 193 2 39 2 3 10 6 eMIOS Output Channel External Interrupt Request FlexCAN Receive Data GPIO EMIOS 15 _IRQ 1 _CNRXD_GPIO 194 2 3...

Page 22: ...lock Synthesizer Signals 2 42 2 3 13 1 Crystal Oscillator Output XTAL 2 42 2 3 13 2 Crystal Oscillator Input External Clock Input EXTAL_EXTCLK 2 42 2 3 13 3 System Clock Output CLKOUT 2 42 2 3 13 4 En...

Page 23: ...am 3 2 3 1 2 Overview 3 3 3 1 3 Features 3 3 3 1 3 1 Instruction Unit Features 3 4 3 1 3 2 Integer Unit Features 3 4 3 1 3 3 Load Store Unit Features 3 4 3 1 3 4 MMU Features 3 5 3 1 3 5 L1 Cache Feat...

Page 24: ...ies 3 32 3 3 6 Signal Processing Extension APU SPE APU 3 33 3 3 7 SPE Programming Model 3 33 3 4 External References 3 34 3 5 Power Architecture Instruction Extensions VLE 3 34 Chapter 4 Reset 4 1 Int...

Page 25: ...4 4 4 Reset Configuration Timing 4 16 4 4 5 Reset Flow 4 18 Chapter 5 Peripheral Bridge PBRIDGE A and PBRIDGE B 5 1 Introduction 5 1 5 1 1 Block Diagram 5 1 5 1 2 Access Protections 5 1 5 1 3 Feature...

Page 26: ...ble Register SIU_IREER 6 20 6 3 1 10 IRQ Falling Edge Event Enable Register SIU_IFEER 6 20 6 3 1 11 IRQ Digital Filter Register SIU_IDFR 6 21 6 3 1 12 Pad Configuration Registers SIU_PCR 6 22 6 3 1 13...

Page 27: ...U_PCR84 6 46 6 3 1 51 Pad Configuration Register 85 SIU_PCR85 6 46 6 3 1 52 Pad Configuration Register 86 SIU_PCR86 6 47 6 3 1 53 Pad Configuration Register 87 SIU_PCR87 6 48 6 3 1 54 Pad Configuratio...

Page 28: ...r 146 SIU_PCR146 6 75 6 3 1 97 Pad Configuration Registers 147 162 SIU_PCR147 SIU_PCR162 6 76 6 3 1 98 Pad Configuration Registers 163 SIU_PCR163 SIU_PCR166 6 77 6 3 1 99 Pad Configuration Registers 1...

Page 29: ...on Register 263 SIU_PCR263 6 99 6 3 1 142 Pad Configuration Register 264 SIU_PCR264 6 99 6 3 1 143 Pad Configuration Register 265 SIU_PCR265 6 100 6 3 1 144 Pad Configuration Register 266 SIU_PCR266 6...

Page 30: ...upt Input Multiplexing 6 124 6 4 5 3 Multiplexed Inputs for DSPI Multiple Transfer Operation 6 124 Chapter 7 Crossbar Switch XBAR 7 1 Introduction 7 1 7 1 1 Block Diagram 7 1 7 1 2 Overview 7 2 7 1 3...

Page 31: ...15 RAM ECC Data Low Registers ECSM_REDRL 8 14 8 3 Initialization and Application Information 8 15 Chapter 9 Enhanced Direct Memory Access eDMA 9 1 Introduction 9 1 9 1 1 Features 9 2 9 1 2 Modes of O...

Page 32: ...9 45 9 4 4 4 Fixed Group Arbitration Round Robin Channel Arbitration 9 46 9 4 5 DMA Transfer 9 46 9 4 5 1 Single Request 9 46 9 4 5 2 Multiple Requests 9 47 9 4 5 3 Modulo Feature 9 49 9 4 6 TCD Statu...

Page 33: ...Hardware Vector Mode Handshaking 10 32 10 5 Initialization and Application Information 10 33 10 5 1 Initialization Flow 10 33 10 5 2 Interrupt Exception Handler 10 33 10 5 2 1 Software Vector Mode 10...

Page 34: ...19 11 4 1 1 Overview 11 19 11 4 1 2 Software Controlled Power Management Clock Gating 11 20 11 4 1 3 Clock Dividers 11 20 11 4 1 3 1External Bus Clock CLKOUT 11 21 11 4 1 3 2Nexus Message Clock MCKO 1...

Page 35: ...9 12 2 1 9 Transfer Error Acknowledge TEA 12 9 12 2 1 10 Transfer Start TS 12 9 12 2 1 11 Write Byte Enables WE BE 12 9 12 2 1 12 Bus Busy BB 12 10 12 2 1 13 Bus Grant BG 12 10 12 2 1 14 Bus Request B...

Page 36: ...2 25 12 4 1 17 Compatible with MPC5xx External Bus with Some Limitations 12 25 12 4 1 18 Misaligned Access Support 12 26 12 4 1 18 1Misaligned Access Support 32 bit 12 26 12 4 2 External Bus Operation...

Page 37: ...ignal Description 13 4 13 2 1 Voltage for Flash Only VFLASH 13 4 13 2 2 Program and Erase Voltage for Flash Only VPP 13 4 13 3 Memory Map and Register Description 13 4 13 3 1 Flash Memory Map 13 6 13...

Page 38: ...2 4 1Flash Erase Suspend Resume 13 31 13 4 2 5 Flash Shadow Block 13 34 13 4 2 6 Censorship 13 34 13 4 2 6 1Censorship Control Word 13 34 13 4 2 6 2Flash Disable 13 35 13 4 2 6 3FLASH_BIUAPR Modifica...

Page 39: ...9Receive Control Register RCR 15 19 15 3 4 2 10Transmit Control Register TCR 15 21 15 3 4 2 11Physical Address Low Register PALR 15 22 15 3 4 2 12Physical Address Upper Register PAUR 15 23 15 3 4 2 13...

Page 40: ...5 Buffer Descriptors 15 44 15 5 1 Driver DMA Operation with Buffer Descriptors 15 44 15 5 1 1 Driver DMA Operation with Transmit BDs 15 45 15 5 1 2 Driver and DMA Operations with Receive BDs 15 45 15...

Page 41: ...3 Memory Map Register Definition 17 6 17 3 1 Register Description 17 8 17 3 1 1 eMIOS Module Configuration Register EMIOS_MCR 17 8 17 3 1 2 eMIOS Global Flag Register EMIOS_GFR 17 9 17 3 1 3 eMIOS Ou...

Page 42: ...15Modulus Counter Buffered Mode MCB 17 57 17 4 4 4 16Output Pulse Width and Frequency Modulation Buffered Mode OPW FMB 17 60 17 4 4 4 17Center Aligned Output Pulse Width Modulation Buffered Mode OP WM...

Page 43: ...TCR2 Visibility Register ETPU_TB2R 18 31 18 4 4 4 STAC Bus Configuration Register ETPU_REDCR 18 32 18 4 5 Global Channel Registers 18 33 18 4 5 1 eTPU Channel Interrupt Status Register ETPU_CISR 18 3...

Page 44: ...IFO Status Register EQADC_CFSR 19 30 19 3 2 12 eQADC SSI Control Register EQADC_SSICR 19 31 19 3 2 13 eQADC SSI Receive Data Register EQADC_SSIRDR 19 33 19 3 2 14 eQADC CFIFO Registers EQADC_CF 0 5 Rn...

Page 45: ...ck and Conversion Speed 19 86 19 4 5 3 Time Stamp Feature 19 89 19 4 5 4 ADC Calibration Feature 19 89 19 4 5 4 1Calibration Overview 19 89 19 4 5 4 2MAC Unit and Operand Data Format 19 90 19 4 5 5 AD...

Page 46: ...2 2 Signals and Descriptions 20 6 20 2 2 1 Peripheral Chip Select Slave Select PCSx 0 _SS 20 6 20 2 2 2 Peripheral Chip Selects 1 3 PCSx 1 3 20 6 20 2 2 3 Peripheral Chip Select 4 Master Trigger PCSx...

Page 47: ...20 4 3 5 Using the RX FIFO Buffering Mechanism 20 39 20 4 3 5 1Filling the RX FIFO 20 39 20 4 3 5 2Draining the RX FIFO 20 40 20 4 4 Deserial Serial Interface DSI Configuration 20 40 20 4 4 1 DSI Mas...

Page 48: ...FO Fill Interrupt or DMA Request TFFF 20 65 20 4 9 3 Transfer Complete Interrupt Request TCF 20 65 20 4 9 4 Transmit FIFO Underflow Interrupt Request TFUF 20 66 20 4 9 5 Receive FIFO Drain Interrupt o...

Page 49: ...rmat 21 19 21 4 3 Baud Rate Generation 21 20 21 4 4 Transmitter 21 21 21 4 4 1 Transmitter Character Length 21 21 21 4 4 2 Character Transmission 21 21 21 4 4 3 Break Characters 21 23 21 4 4 4 Idle Ch...

Page 50: ...emory Map 22 6 22 3 2 Message Buffer Structure 22 7 22 3 3 Register Descriptions 22 9 22 3 3 1 Module Configuration Register CANx_MCR 22 10 22 3 3 2 Control Register CANx_CR 22 12 22 3 3 3 Free Runnin...

Page 51: ...22 34 22 5 Initialization and Application Information 22 34 22 5 1 FlexCAN2 Initialization Sequence 22 34 22 5 2 FlexCAN2 Addressing and RAM Size 22 35 Chapter 23 Voltage Regulator Controller VRC and...

Page 52: ...guration 24 6 24 4 2 IEEE 1149 1 2001 JTAG Test Access Port 24 6 24 4 3 TAP Controller State Machine 24 6 24 4 3 1 Enabling the TAP Controller 24 8 24 4 3 2 Selecting an IEEE 1149 1 2001 Register 24 8...

Page 53: ...4 4 Nexus Messaging 25 12 25 4 5 System Clock Locked Indication 25 12 25 5 Nexus Port Controller NPC 25 13 25 5 1 Overview 25 13 25 5 2 Features 25 13 25 6 Memory Map Register Definition 25 13 25 6 1...

Page 54: ...11 8 Data Trace Control Register DTC 25 43 25 11 9 Data Trace Start Address Registers 1 and 2 DTSAn 25 44 25 11 10 Data Trace End Address Registers 1 and 2 DTEAn 25 44 25 11 11 NZ6C3 Register Access...

Page 55: ...ight MDO Configuration 25 62 25 14 7 Watchpoint Support 25 63 25 14 7 1 Overview 25 63 25 14 7 2 Watchpoint Messaging 25 63 25 14 7 3 Watchpoint Error Message 25 64 25 14 7 4 Watchpoint Timing Diagram...

Page 56: ...25 17 2 11 IEEE 1149 1 JTAG Test Access Port 25 82 25 17 2 11 1 NXDM JTAG DID Register 25 83 25 17 2 11 2Enabling the NXDM TAP Controller 25 83 25 17 2 11 3 NXDM Register Access via JTAG 25 83 25 17 3...

Page 57: ...on Chip Selects 0 through 3 B 4 B 4 2 Pad Ring B 4 B 4 3 CLKOUT B 5 B 5 Packaging B 5 B 6 Power Supplies B 5 B 7 Integration Logic Functionality B 5 B 8 Application Information B 6 B 8 1 Enabling Cali...

Page 58: ...SRAM Flash 3 MB flash memory The fastest accesses are to the unified cache Both the internal SRAM and the flash memory hold instructions and data The external bus interface is designed to support mos...

Page 59: ...The internal multiplexer submodule SIU_DISR provides multiplexing of eQADC trigger sources daisy chaining the DSPIs and external interrupt signal multiplexing The Fast Ethernet FEC module is a RISC ba...

Page 60: ...register JTAG JTAG controller LSU Load store unit MMU Memory management unit PCU Program counter unit SPE Signal processing engine SPR Special purpose register TB Time base VLE Variable length encodin...

Page 61: ...ysteresis Selectable hysteresis Selectable slew rate control External bus support 1 62 3 6 V operation and Nexus pins support 2 5 3 6 V operation Selectable drive strength control Unused pins configur...

Page 62: ...sbar switch XBAR Four master ports five slave ports 32 bit address bus 64 bit data bus Simultaneous accesses from different masters to different slaves there is no clock penalty when a parked master a...

Page 63: ...bus the 496 pin VertiCal assembly has the calibration functionality Memory controller with support for various memory types Non burst SDR flash and SRAM Asynchronous and legacy flash and SRAM Most st...

Page 64: ...rapid end of line programming Hardware programming state machine Configurable cache memory 0 32 KB 4 and 8 way set associative unified instruction and data cache Decouples processor performance from...

Page 65: ...ue modes with priority based preemption initiated by software command internal eTPU and eMIOS or external triggers DMA and interrupt request support Supports all functional modes from QADC MPC5xx fami...

Page 66: ...atibility with previous FlexCAN modules Nexus development interface NDI Per IEEE ISTO 5001 2003 Real time development support for Power Architecture core and the eTPU engines through Nexus class 3 som...

Page 67: ...ller Fully software compatible to the FEC module of Freescale s industry standard PowerQUICC communications controller Full compliance with the IEEE 802 3 standard for 10 100 base T Support for differ...

Page 68: ...ass 3 NZ6C3 SRAM KB 64 128 Flash memory Main array MB 2 3 3 Shadow block KB 1 1 External bus interface EBI Data 32 bit 32 bit 4 Address 24 bit 24 bit 5 Calibration bus interface CBI Y Enhanced direct...

Page 69: ...0 channel ADC 0 Y Y ADC 1 Y Y Fast Ethernet controller FEC Y 8 FlexRay FlexRay Nexus Frequency modulated phase lock loop FMPLL Y Y Maximum system frequency9 132 MHz 147 MHz Crystal range 8 20 MHz 8 20...

Page 70: ...tching have an effective execution time of one clock Memory load and store operations are provided for byte halfword word 32 bits and doubleword 64 bits data with automatic zero or sign extension of b...

Page 71: ...ted access 1 5 3 Enhanced Direct Memory Access eDMA The enhanced direct memory access eDMA controller is a second generation module capable of performing complex data movements via 64 programmable cha...

Page 72: ...The EBI is available on the 416 BGA package only The EBI also enables an external master to access internal address space The EBI includes a memory controller that generates interface signals to supp...

Page 73: ...oherency with other possible bus masters Both instruction and data accesses are performed using a single bus connected to the cache The processor uses virtual addresses to index the cache array The me...

Page 74: ...liminated In the MCU the TPU engine is combined with shared instruction and data RAM to form a powerful time processing subsystem The MPC5566 has two eTPU engines You can use the high level assembler...

Page 75: ...CAN protocol according to CAN Specification version 2 0B The CAN protocol is designed to be used primarily as a vehicle serial data bus meeting the specific requirements of this field real time proces...

Page 76: ...andard Support for full duplex operation 200 Mbps throughput with a system clock of 100 MHz Support for half duplex operation 100 Mbps throughput with a system clock of 50 MHz IEEE 802 3 full duplex f...

Page 77: ...o prevent corruption Table 1 2 shows a detailed list of the device memory map Table 1 2 MPC5566 Detailed Memory Map Address Range1 Allocated Size1 bytes Used Size bytes Use 0x0000_0000 0x002F_FFFF 3 M...

Page 78: ...FFFF 192 KB N A Reserved 0xFFF4_0000 0xFFF4_3FFF 16 KB N A ECSM 0xFFF4_4000 0xFFF4_7FFF 16 KB N A DMA controllers 2 eDMA 0xFFF4_8000 0xFFF4_BFFF 16 KB N A Interrupt controller INTC 0xFFF4_C000 0xFFF4_...

Page 79: ...to 0x2FFF_FFFF and Calibration memory ranges from 0x3000_0000 to 0x3FFF_FFFF Hardware does not force any restrictions on allocating memory to the EBI versus calibration bus 3 The FEC pins are muxed wi...

Page 80: ...0x007F_FFFF 2 This address range is not part of the MPC5500 family slave memory map rather it is shown to illustrate the addressing scheme for off chip accesses in multi master mode 8 MB N A Used for...

Page 81: ...Introduction MPC5566 Microcontroller Reference Manual Rev 2 1 24 Freescale Semiconductor...

Page 82: ...eature set and compatibility between the MPC5500 devices most of the balls have multiplexed signal functions Primary signal functions that are not available on the device but are used as pin labels in...

Page 83: ...N2 _AN 5 DAN3 _AN 6 DAN3 _AN 7 ANW_AN 8 ANX_AN 9 ANY_AN 10 ANZ_AN 11 SDS_MA 0 _AN 12 SDO_MA 1 _AN 13 SDI_MA 2 _AN 14 FCK_AN 15 AN 16 39 TCRCLKA_IRQ 7 _GPIO 113 ETPUA 0 11 _ETPUA 12 23 _GPIO 114 125 ET...

Page 84: ...signal function name is used in the Ball Grid Array BGA map to identify the location of the ball however the primary signal function is not always valid for all devices As shown in Figure 2 2 when th...

Page 85: ...LLMRFM mode selection External interrupt request GPIO P A G I I I O VDDEH6 MH PLLCFG Up Up AB25 AB27 PLLCFG 1 _ IRQ 5 _ SOUTD_ GPIO 209 PLLMRFM reference selection External interrupt request DSPI D da...

Page 86: ...B4 AB3 U1 V2 V1 W2 W1 Y2 Y1 AA2 AA1 AB2 AC1 Y7 AC3 AC5 AB5 T3 T2 T1 V2 W1 W2 Y1 Y2 AA2 AB2 AC2 ADDR 27 29 _ 10 GPIO 23 25 External address bus GPIO P G I O I O VDDE2 F Up Up 11 AC2 AD1 AE1 AD2 3 AD1 A...

Page 87: ...xternal data bus Ethernet receive data valid GPIO P A G I O I I O VDDE3 F Up Up 11 AD6 AF6 DATA 26 _ 10 FEC_TX_EN_ GPIO 54 External data bus Ethernet transmit enable GPIO P A G I O O I O VDDE3 F Up Up...

Page 88: ...3 AF17 BG_ FEC_MDIO_ GPIO 73 External bus grant Ethernet management data I O GPIO P A G I O I O I O VDDE3 F Up Up 11 AE14 AG16 BB_ GPIO 74 External bus busy GPIO P G I O I O VDDE3 F Up Up 11 AF14 AG17...

Page 89: ...k input P I VDDE7 F TCK Down TCK Down D25 E27 TDI JTAG test data input P I VDDE7 F TDI Up TDI Up D26 E28 TDO JTAG test data output P O VDDE7 F TDO Up17 TDO Up E25 F27 TMS JTAG test mode select input P...

Page 90: ...GPIO P A G I O I O VDDEH6 MH Up Up R25 P27 SOUTA_ PCSC 5 _ GPIO 95 DSPI A data output DSPI C peripheral chip select GPIO P A G O O I O VDDEH6 MH Up Up R24 P24 PCSA 0 _ PCSD 2 _ GPIO 96 DSPI A periphe...

Page 91: ...ct DSPI C clock GPIO P A G O I O I O VDDEH6 MH Up Up P24 N27 PCSB 5 _ 19 PCSC 0 _ GPIO 110 DSPI B peripheral chip select DSPI C peripheral chip select GPIO P A G O I O I O VDDEH6 MH Up Up R23 M26 eQAD...

Page 92: ...ngle ended analog input P I VDDA1 20 A I AN 16 18 A6 C5 D8 B7 E8 H12 AN 19 20 Single ended analog input P I VDDA1 20 A I AN 19 20 B5 B6 C7 C8 AN 21 25 Single ended analog input P I VDDA0 20 A I AN 21...

Page 93: ...PCSB 5 _ GPIO 129 eTPU A channel DSPI B peripheral chip select GPIO P A G I O O I O VDDEH1 MH WKPCFG WKPCFG J2 H3 ETPUA 16 _ PCSD 1 _ GPIO 130 eTPU A channel DSPI D peripheral chip select GPIO P A G I...

Page 94: ...PCSA 2 _ GPIO 164 eTPU B channel DSPI A peripheral chip select GPIO P A G I O O I O VDDEH8 MH WKPCFG WKPCFG D17 E19 ETPUB 18 _ PCSA 3 _ GPIO 165 eTPU B channel DSPI A peripheral chip select GPIO P A G...

Page 95: ...0 _ GPIO 195 eMIOS channel eTPU B channel output only GPIO P A G I O O I O VDDEH4 SH WKPCFG WKPCFG AE19 AG19 EMIOS 17 _ ETPUB 1 _ GPIO 196 eMIOS channel eTPU B channel output only GPIO P A G I O O I...

Page 96: ...regulator control output P O 3 3 V VDDINT N A VRCCTL AB24 AC26 VDDA0 32 Analog power input ADC0 P I 5 0 V VDDINT N A VDDA0 C14 E15 VSSA0 32 Analog ground input ADC0 P I VSSINT N A VSSA0 A14 B14 A15 B1...

Page 97: ...J21 L15 L16 L17 L18 M18 N18 P18 VDDE12 External I O supply input P I 1 8 3 3 V VDDE N A VDDE K7 N8 R11 R12 R13 R17 R18 R21 T11 T12 T15 T18 U2 U11 U15 U16 V15 V16 V17 V22 AA13 AA16 AB18 AB21 AE2 AG4 A...

Page 98: ...10 power supply with the exception of the VDDE2 and VDDE3 segments that are shorted together and must use the same power supply input This segment is labeled VDDE2 in the BGA map 3 The pad type is in...

Page 99: ...from the same power supply 3 5 25 V To allow one DSPI to operate at a different operating voltage connect VDDEH6 and VDDEH10 to separate power supplies but this configuration is not compatible with th...

Page 100: ...Interrupt Request GPIO PLLCFG 0 _IRQ 4 _GPIO 208 PLLCFG 0 _IRQ 4 _GPIO 208 are sampled on the negation of the RESET input pin if the RSTCFG pin is asserted at that time The values are used to configu...

Page 101: ...the device The alternate functions are the external interrupt request inputs IRQs 2 3 1 8 Weak Pull Configuration GPIO WKPCFG_GPIO 213 WKPCFG_GPIO 213 determines whether specified eTPU and eMIOS pins...

Page 102: ...8 External Data Ethernet Carrier Sense Data GPIO DATA 17 _FEC_CRS_GPIO 45 DATA 17 _FEC_CRS_GPIO 45 is an EBI data signal The alternate signal is FEC carrier sense data function 2 3 2 9 External Data...

Page 103: ...a Ethernet Receive Data Valid GPIO DATA 25 _FEC_RX_DV_GPIO 53 DATA 25 _FEC_RX_DV_GPIO 53 is an EBI data signal The alternate function is an FEC receive data valid function 2 3 2 17 External Data Ether...

Page 104: ...y the EBI in single master operation 2 3 2 24 External Read Write GPIO RD_WR_GPIO 62 RD_WR_GPIO 62 indicates whether an external bus transfer is a read or write operation 2 3 2 25 External Burst Data...

Page 105: ...BG_FEC_MDIO_GPIO 73 BG_FEC_MDIO_GPIO 73 is the bus grant The secondary function is the Ethernet management data I O FEC_MDIO 2 3 2 33 External Bus Busy GPIO BB_GPIO 74 BB_GPIO 74 is the external bus...

Page 106: ...2 75 are the trace message outputs to the development tools for full port mode These pins function as GPIO when the Nexus port controller NPC operates in reduced port mode 2 3 3 7 Nexus Message Start...

Page 107: ...the eSCI A module 2 3 5 2 FlexCAN A Receive eSCI A Receive GPIO CNRXA_RXDA_GPIO 84 CNRXA_RXDA_GPIO 84 is the receive pin for the FlexCAN A module The alternate function is the receive pin for the eSC...

Page 108: ...DSPI D GPIO TXDB_PCSD 1 _GPIO 91 TXDB_PCSD 1 _GPIO 91 is the transmit pin for the eSCI B module The alternate function is a peripheral chip select output for the DSPI D module 2 3 6 4 eSCI B Receive...

Page 109: ...on is PCSB 2 a peripheral chip select for the DSPI B module 2 3 7 6 DSPI A DSPI D Clock GPIO PCSA 2 _SCKD_GPIO 98 PCSA 2 _SCKD_GPIO 98 The PCSA 2 is the primary function and is a peripheral chip selec...

Page 110: ...he primary function and is a DSPI B peripheral chip select output pin It also is a Slave Select SS input pin for the DSPI B module slave mode operation The alternate function is PCSD 2 and is a chip s...

Page 111: ...ntial Analog Input AN 0 _DAN0 AN 0 is a single ended analog input to the two on chip ADCs DAN0 is the positive terminal of the differential analog input DAN0 DAN0 to DAN0 2 3 8 2 Analog Input Differen...

Page 112: ...chip ADCs DAN3 is the negative terminal of the differential analog input DAN3 DAN3 to DAN3 2 3 8 9 Analog Input Multiplexed Analog Input AN 8 _ANW AN 8 is an analog input pin ANW is an analog input in...

Page 113: ...r the eQADC SSI this function is selected by setting the PA field of SIU_PCR216 to GPIO This pin has reduced analog to digital conversion accuracy as compared to the AN 0 7 and AN 16 39 analog input p...

Page 114: ...and CFIFO4 ETRIG 1 serves as the external trigger for CFIFO1 CFIFO3 and CFIFO5 GPIO 111 112 are general purpose input output functions 2 3 8 19 Voltage Reference High VRH VRH is the voltage reference...

Page 115: ...PIO 116 is an input output channel pin for the eTPU A module ETPUA 2 is the primary function and is an input output channel for the eTPU A module The alternate function is an output channel for the eT...

Page 116: ...20 the pin functions as output only 2 3 9 11 eTPU A Channel eTPU A Output Channel GPIO ETPUA 9 _ETPUA 21 _GPIO 123 ETPUA 9 _ETPUA 21 _GPIO 123 is an input output channel pin for the eTPU A module The...

Page 117: ...1 _GPIO 130 is an input output channel pin for the eTPU A module The alternate function is a peripheral chip select for the DSPI D module 2 3 9 19 eTPU A Channel DSPI D GPIO ETPUA 17 _PCSD 2 _GPIO 13...

Page 118: ...24 27 _IRQ 12 15 _GPIO 138 141 ETPUA 24 27 _IRQ 12 15 _GPIO 138 141 are output channel pins for the eTPU A module The alternate functions are external interrupt request inputs for the SIU module 2 3...

Page 119: ...e functions are peripheral chip select signals for DSPI A 2 3 9 34 eTPU B Channel GPIO ETPUB 20 31 _GPIO 167 178 ETPUB 20 31 _GPIO 167 178 are input output channel pins for the eTPU B module 2 3 10 En...

Page 120: ...t channel pin for the eMIOS module The alternate function is an external interrupt request input and the secondary alternate function is the FlexCAN receive data 2 3 10 7 eMIOS Channel eTPU B Output C...

Page 121: ...annel GPIO EMIOS 14 15 _GPIO 203 204 The EMIOS 14 15 _GPIO 203 204 pins primary function is EMIOS 14 15 When configured as EMIOS 14 15 the pins function as output channels for the eMIOS module Because...

Page 122: ...Address CAL_ADDR 12 30 CAL_ADDR 12 30 are the calibration addresses They are functional only when using the 496 pin assembly 2 3 12 4 Calibration Data CAL_DATA 0 15 CAL_DATA 0 15 is the primary funct...

Page 123: ...ternal clock input The function of this pin is determined by the PLLCFG configuration pins 2 3 13 3 System Clock Output CLKOUT CLKOUT is the device system clock output 2 3 13 4 Engineering Clock Outpu...

Page 124: ...SYN VSSSYN is the ground reference input for the FMPLL 2 3 14 8 Flash Read Supply Input VFLASH VFLASH is the on chip Flash read supply input 2 3 14 9 Flash Program Erase Supply Input VPP VPP is the on...

Page 125: ...configured for its primary function or GPIO Table 2 2 MPC5566 Device Power Ground Segmentation Power Segment Voltage Range1 I O Pins Powered by Segment VDDA0 5 0 V AN 21 35 REFBYPC VRH VDDA1 5 0 V AN...

Page 126: ...AN 10 _ANY AN 11 _ANZ AN 16 21 AN 36 39 VSSA0 GND VSSA0 VSSA1 GND VSSA1 VDDE2 1 8 3 3 V CS 0 CS 1 3 _ADDR 9 11 _GPIO 1 3 ADDR 8 29 _GPIO 4 25 ADDR 30 31 _ADDR 6 7 _GPIO 26 27 RD_WR_GPIO 62 BDIP_GPIO...

Page 127: ..._IRQ 5 _SOUTD_GPIO 209 RSTCFG_GPIO 210 BOOTCFG 0 _IRQ 2 _GPIO 211 BOOTCFG 1 _IRQ 3 _GPIO 212 WKPCFG_GPIO 213 CNTXC_PCSD 3 _GPIO 87 CNRXC_PCSD 4 _GPIO 88 TXDA_GPIO 89 RXDA_GPIO 90 TXDB_PCSD 1 _GPIO 91...

Page 128: ...pin only A diagram for the ETPUA 0 15 to SOUTC connection is given in Figure 2 4 Figure 2 4 ETPUA 0 15 DSPI C I O Connections 2 VDDE2 and VDDE3 are separate segments in the device pad ring These segme...

Page 129: ...or ETPUA16 and applies to ETPUA 16 21 Figure 2 6 shows the connections for ETPUA24 and applies to TPUA 24 29 The full ETPUA to DSPI B connections are given in Table 2 5 and ETPU A to DSPI D in Table 2...

Page 130: ...eMIOS channels DSPI B serialized output channels 14 15 are connected to eMIOS channels DSPI B serialized output channels 0 through 7 are not connected eTPU A Channel Output eTPU A Channel Input 13 24...

Page 131: ...re multiplexed on the ETPUB 0 15 pins The outputs of ETPUB 0 7 are multiplexed on the eMIOS 16 23 pins so that the output channels of ETPUB 0 7 can be used when the normal pins for these channels are...

Page 132: ...ble 2 7 ETPUB 0 15 DSPI A I O Mapping DSPI A Serialized Inputs eTPU B Channel Output 15 0 14 1 13 2 12 3 11 4 10 5 9 6 eTPU B CH16 CH0 CH24 CH15 IN 15 IN 8 IN 7 IN 0 DSPI A ETPUB 15 _ ETPUB 31 CH23 CH...

Page 133: ...are unidirectional as output only The output channels of EMIOS 10 13 can be serialized OUT and the inputs of EMIOS 12 15 can be serialized IN The DSPI connections for EMIOS 10 11 are given in Figure...

Page 134: ...Figure 2 10 EMIOS 14 15 DSPI D I O Connections CH13 IN CH13 OUT IN 14 IN 9 DSPI B DSPI D OUT 14 eMIOS CH12 IN CH12 OUT EMIOS 13 _ SOUTD_ GPIO 192 EMIOS 12 _ SOUTC_ GPIO 191 IN 8 OUT 15 IN 15 CH15 IN C...

Page 135: ...Signal Description MPC5566 Microcontroller Reference Manual Rev 2 2 54 Freescale Semiconductor...

Page 136: ...s that implement versions built on the Power Architecture embedded category The host processor core of the device complies with the Power Architecture embedded category which is 100 percent user mode...

Page 137: ...3 1 e200z6 Block Diagram CPU Control Logic Load 32 KB Cache Data Memory Management Unit Address Store Unit Control Instruction Unit Address Branch Unit PC Unit Instruction Buffer GPRs CR SPR Multiply...

Page 138: ...These instructions operate on 16 bit or 32 bit data types and produce vector or scalar results In addition to the base Power Architecture instruction set the e200z6 core also implements the VLE Varia...

Page 139: ...tion of successful lookahead branches 3 1 3 2 Integer Unit Features The integer unit supports single cycle execution of most integer instructions 32 bit AU for arithmetic and comparison operations 32...

Page 140: ...che power usage can be minimized 3 1 3 6 BIU Features The features of the e200z6 BIU are as follows 32 bit address bus plus attributes and control Separate unidirectional 64 bit read data bus and 64 b...

Page 141: ...the results of certain operations such as move integer and floating point compare arithmetic and logical instructions and provide a mechanism for testing and branching Vectored and auto vectored inter...

Page 142: ...operate on the entire 64 bit register The SPE APU defines load and store instructions for transferring 64 bit values to from memory Figure 3 2 and Figure 3 3 show the complete e200z6 register set Figu...

Page 143: ...86 DECAR SPR 54 IVOR0 IVOR1 IVOR15 SPR 400 SPR 401 SPR 415 Interrupt Vector Prefix IVPR SPR 63 Interrupt Vector Offset Debug Registers 2 Context Control 1 Debug Control DBCR0 DBCR1 DBCR2 DBCR3 1 SPR 3...

Page 144: ...te on the entire 64 bit register Condition register CR The 32 bit CR consists of eight 4 bit fields CR0 CR7 that reflect results of certain arithmetic operations and provide a mechanism for testing an...

Page 145: ...er MSR The MSR defines the state of the processor The MSR can be modified by the move to machine state register mtmsr system call sc and return from exception rfi rfci rfdi instructions It can be read...

Page 146: ...Debug status register DBSR This register contains debug event status Instruction address compare registers IAC1 IAC4 These registers contain addresses and or masks which are used to specify instructi...

Page 147: ...ory registers described previously Configuration registers Hardware implementation dependent 0 HID0 controls processor and system functions Hardware implementation dependent 1 HID1 controls processor...

Page 148: ...TLBs System version register SVR is a read only and identifies the version model and revision level of the system with an e200z6 processor built on the Power Architecture embedded category For more de...

Page 149: ...he result constitutes the physical address of the access Table 3 2 shows the TLB entry bit definitions PVR value Least significant halfword of processor version register PVR is 0x0000 that contains th...

Page 150: ...f the effective address plus the address space bit matches the EPN field and TS bit of the TLB entry that TLB entry is a candidate for a possible translation match In addition to a match in the EPN fi...

Page 151: ...execute only and data structures can be mapped as read write no execute The following access control bits support selective permissions for access control SR Supervisor read permission Allows loads an...

Page 152: ...g writing and searching the TLBs The MAS registers can be read or written using the mfspr and mtspr instructions The e200z6 does not implement the MAS5 register present in other Freescale EIS designs...

Page 153: ...0 31 R VALID IPROT TID TS TSIZE W Reset Undefined on Power Up Unchanged on Reset Figure 3 8 MMU Assist Register 1 MAS 1 Table 3 4 MAS 1 Descriptor Context and Configuration Control Field Description 0...

Page 154: ...t Register 2 MAS 2 Table 3 5 MAS 2 EPN and Page Attributes Field Description 0 19 EPN Effective page number 0 19 20 25 Reserved must be cleared 26 VLE Power Architecture VLE 0 This page is a standard...

Page 155: ...r 1 The page is accessed in true little endian byte order SPR 627 Access R W Permission Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R RPN U0 U1 U2 U3 UX...

Page 156: ...TIDSELD Default PID to load TID from 00 PID0 01 Reserved do not use 10 Reserved do not use 11 TIDZ 0x00 Use all zeros the globally shared value 16 19 Reserved must be cleared 20 23 TSIZED Default TSIZ...

Page 157: ...nected to the cache Addresses from the processor to the cache are virtual addresses used to index the cache array The MMU provides the virtual to physical translation for use in performing the cache t...

Page 158: ...critical doubleword first The line is fetched and placed into the appropriate cache block and the critical doubleword is forwarded to the CPU Subsequent doublewords can be streamed to the CPU if they...

Page 159: ...dware reset a hardware reset does not invalidate the cache lines Following initial power up the cache contents are undefined If the L D or V bits are set on any lines the software must invalidate cach...

Page 160: ...n The device provides additional user control over cache power utilization via the L1CSR0 WID AWID WDD and AWDD way disable bits and the L1CSR0 WAM control bit When WAM is set to 1 ways that are disab...

Page 161: ...ister is shown in Figure 3 16 The correct sequence necessary to change the value of LSCSR0 is 1 msync 2 isync 3 mtspr L1CSR0 The L1CSR0 bits are described in Table 3 9 0 1 2 3 4 5 6 7 8 9 10 11 12 13...

Page 162: ...dditional ways When configured as a 4 way cache this bit is ignored 10 WAM Way access mode 0 Disable way access is checked not enabled for replacement on an access type are still checked for a cache h...

Page 163: ...ndefined operation Writing a 0 during a flash clear operation is ignored Cache lock bits flash clear operations require approximately 134 cycles to complete Clearing occurs regardless of the enable CE...

Page 164: ...7 28 29 30 31 CARCH CWPA CFAHA CFISWA 0 CBSIZE CREPL CLA CPA CNWAY CSIZE 01 1 0 1 0 0 00 10 1 1 00000111 8 way 00000011 4 way 00000100000 32 KB SPR 515 Read only Figure 3 17 L1 Cache Configuration Reg...

Page 165: ...reset none vector to 0xFFFF_FFFC Reset by assertion of RESET Watchdog timer reset control Debug reset control Critical input IVOR 0 IVOR 0 is not supported in the device Machine check IVOR 1 ME CSSR...

Page 166: ...1 MSR FP 0 and attempt to execute a Book E floating point operation System call IVOR 8 SRR 0 1 Execution of the system call sc instruction AP unavailable IVOR 9 SRR 0 1 Unused by e200z6 Decrementer I...

Page 167: ...nated to provide a long period 64 bit counter Debug IVOR 15 DE IDM CSSR 0 1 Debugger when HIDO DAPUEN 0 Caused by trap instruction address compare data address compare instruction complete branch take...

Page 168: ...4 bit scalar result Vector fixed point instructions operate on a vector of two 32 bit or four 16 bit fixed point numbers resident in the 64 bit GPRs Vector floating point instructions operate on a vec...

Page 169: ...Reference Manual e200z6 with VLE Errata to e200z6 PowerPCTM Core Reference Manual Rev 0 3 5 Power Architecture Instruction Extensions VLE The variable length encoding VLE provides an extension to 32 b...

Page 170: ...utput RSTOUT For all reset sources the BOOTCFG 0 1 and PLLCFG 0 1 signals can be used to determine the boot mode and the configuration of the FMPLL respectively If the RSTCFG pin is asserted during re...

Page 171: ...t RESET The RESET pin is an active low input that is asserted by an external device during a power on or external reset The internal reset signal asserts only if the RESET pin is asserted for 10 clock...

Page 172: ...4 3 Memory Map Register Definition Table 4 1 summarizes the reset controller registers The base address of the system integration unit is 0xC3F9_0000 4 3 1 Register Descriptions This section describes...

Page 173: ...value latched on the pin or pins at the negation of the last reset 3 The RESET value of this bit or field is determined by the value latched on the pin or pins at the negation of the last reset BOOTCF...

Page 174: ...t setting 1 WKPCFG pin latched during the last reset was logic 1 and weak pullup is the default setting 17 28 Reserved 29 30 BOOTCFG Reset configuration pin status Holds the value of the BOOTCFG 0 1 p...

Page 175: ...mined number of clock cycles Refer to Section 4 2 2 Reset Output RSTOUT but the MCU is not reset The bit is automatically cleared when the software external reset completes 0 Do not generate an softwa...

Page 176: ...SET pin must be asserted during a power on reset to guarantee proper operation of the MCU The PLLCFG 0 1 and RSTCFG pins determine the configuration of the FMPLL If the RSTCFG pin is asserted at the n...

Page 177: ...The reset controller then waits four clock cycles before the negating RSTOUT and updating the fields in the SIU_RSR The ERS bit is set and all other reset status bits in the SIU_RSR are cleared Refer...

Page 178: ...of clock 4 4 2 3 5 Watchdog Timer Debug Reset The WDRS bit in the reset status register SIU_RSR is set when the watchdog timer or a debug request reset occurs A watchdog timer reset occurs and the WD...

Page 179: ...the FMPLL is locked the reset controller waits a predetermined number of clock cycles before negating RSTOUT Refer to Section 4 2 2 Reset Output RSTOUT When the clock count finishes the WKPCFG and BOO...

Page 180: ...SIU_SRCR causes the external RSTOUT pin to be asserted for a predetermined number of clocks The SER bit automatically clears after the clock cycle count expires A software external reset does not caus...

Page 181: ...PCFG is latched four clock cycles before RSTOUT negates After reset software can modify the weak pullup down selection for all I O pins through the PCRs in the SIU Refer to Chapter 2 Signal Descriptio...

Page 182: ...Book E code or as Freescale VLE code and if booting externally sets the bus size Refer to the register indicated in RCHW bit descriptions for a description of each control bit NOTE Do not configure th...

Page 183: ...RCHW from either 16 or 32 bit external memories Then the BAM reconfigures the EBI either as a 16 bit bus or a 32 bit bus according to the settings of this bit 0 32 bit CS 0 port size 1 16 bit CS 0 por...

Page 184: ...gram executes which is for every power on external or internal reset event The only exception to this is the software external reset Refer to Section 4 4 3 5 Reset Configuration Halfword for detailed...

Page 185: ...the assertion of RSTOUT The values of the WKPCFG and BOOTCFG 0 1 pins are latched 4 clock cycles before the negation of RSTOUT and stored in the reset status register SIU_RSR BOOTCFG 0 1 are latched...

Page 186: ...nd RSTCFG are 4 clock cycles PLL locked 24001 clock cycles Don t Care and WKPCFG is treated as 1 during POR assertion PLLCFG RSTCFG and WKPCFG are applied but not latched RSTCFG still applied 1 This c...

Page 187: ...Flow The following figure shows the process flow used for an external reset Figure 4 5 External Reset Flow Diagram False True RESET asserted Wait 2 clock cycles False True RESET asserted Set latch wai...

Page 188: ...negated Default PLL configuration applied not latched False True Wait 24001 clock cycles Latch WKPCFG pin RSTCFG asserted Latch BOOTCFG values Wait four clock cycles Update reset status register Negat...

Page 189: ...Reset MPC5566 Microcontroller Reference Manual Rev 2 4 20 Freescale Semiconductor...

Page 190: ...l module selects for peripheral devices on the slave bus interface 5 1 1 Block Diagram The PBRIDGE is the interface between the system bus and on chip peripherals as shown in Figure 5 1 Figure 5 1 PBR...

Page 191: ...ripherals for with each master and slave Refer to Section 13 3 2 9 Flash Bus Interface Unit Access Protection Register FLASH_BIUAPR for more information on access protection Table 5 1 Peripheral Bridg...

Page 192: ...reads and writes are supported to each slave peripheral Supports a pair of slave accesses for 64 bit instruction fetches Provides configurable per module write buffering support Provides configurable...

Page 193: ...0 PBRIDGE_A_PACR0 Peripheral access control register 0 32 Base 0x0024 0x003F Reserved Base 0x0040 PBRIDGE_A_OPACR0 Off platform peripheral access control register 0 32 Base 0x0044 PBRIDGE_A_OPACR1 Off...

Page 194: ...000 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MBW0 MTR0 MTW0 MPL0 MBW1 MTR1 MTW1 MPL1 MBW2 MTR2 MTW2 MPL2 MBW3 MTR3 MTW3 MPL3 W Reset 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 16 17 18 19 20 21 22 23 2...

Page 195: ...e 1 Write accesses from the eDMA are allowed to be buffered 9 MTR2 Master trusted for reads Determines whether the eDMA is trusted for read accesses Trusted by default 0 The eDMA is not trusted for re...

Page 196: ...NOTE Not all members of the MPC5500 family have PBRIDGE_x_PACR and PBRIDGE_x_OPACR On the devices that do not have them writes to their addresses receive a transfer error To ensure code compatibility...

Page 197: ...0 0 1 3 0 0 0 1 3 0 0 0 1 3 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R BW4 SP4 WP4 TP4 BW5 SP5 WP5 TP5 BW6 SP6 WP6 TP6 BW7 SP7 WP7 TP7 W Reset A_PACR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset...

Page 198: ...es Determines whether write accesses to this peripheral are allowed to be buffered Write accesses not bufferable by default 0 No write accesses are bufferable by the PBRIDGE to this peripheral 1 Write...

Page 199: ...ermines whether the peripheral allows accesses from an untrusted master Only trusted master privileges can access this register 0 Accesses from an untrusted master are allowed 1 Accesses from an untru...

Page 200: ...0100 3 0b0100 4 7 0b0000 PBRIDGE_B_OPACR0 PBRIDGE_B_Base 0x0040 0 eQADC 0b0100 1 3 0b0100 4 DSPI A 0b0100 5 DSPI B 0b0100 6 DSPI C 0b0100 7 DSPI D 0b0100 PBRIDGE_B_OPACR1 PBRIDGE_B_Base 0x0044 0 3 0b0...

Page 201: ...proved performance in systems where frequent writes to a slow peripheral occur Write buffering is controllable on a per master and per peripheral basis Enable write buffering for masters and periphera...

Page 202: ...ted If the buffer has valid entries a following read cycle stalls until the buffer is emptied and the read cycle can be completed 5 4 3 General Operation Slave peripherals are modules that contain rea...

Page 203: ...esses to certain slave peripherals or it can allow the individual slave peripherals to determine if user mode accesses are allowed In addition peripherals can be designated as write protected The PBRI...

Page 204: ...and initializes the following controls MCU reset configuration System reset operation Pad configuration External interrupts General purpose I O GPIO Internal peripheral multiplexing 6 1 1 Block Diagra...

Page 205: ...nd peripheral I O channels are external to the SIU Reset RESET configuration SIU registers Reset controller Pad Interface Pad Ring Pad configuration RSTOUT Power on reset detection External IRQ edge d...

Page 206: ...from the set of multiplexed functions Pullup and pulldown characteristics of the pin Slew rate for slow and medium pads Open drain mode for output pins Hysteresis for input pins Drive strength of bus...

Page 207: ...EH input pins Table 6 3 SIU Signal Properties Name Function I O Type Pad Type Pullup Pulldown 1 1 Internal weak pullup down The reset weak pullup down state for the primary signal function is given Fo...

Page 208: ...bit general purpose data input SIU_GPDIn and a general purpose data output SIU_GPDOn register Refer to the following sections for more information Section 6 3 1 159 GPIO Pin Data Output Registers 0 21...

Page 209: ...hat are enabled by setting a bit in IRQ rising edge event enable register SIU_IREER IRQ falling edge event enable register SIU_IFEER If the bit is set in both registers both rising and falling edge ev...

Page 210: ...equest enable register SIU_DIRER Select bit is cleared in the DMA Interrupt select register SIU_DIRSR Refer to the following sections for more information Section 6 3 1 5 DMA Interrupt Request Enable...

Page 211: ...enable bit in the IRQ rising and falling edge event enable registers SIU_IREER SIU_IFEER 2 Clear the enable bits for the DMA Interrupt request enable register SIU_DIRER The IRQ bit is set in the exte...

Page 212: ...D5 SIU_GPDO0 SIU_GPDO213 GPIO pin data output registers 0 213 8 Base 0x06D6 0x07FF Reserved Base 0x0800 0x08D5 SIU_GPDI0 SIU_GPDI213 GPIO pin data input registers 0 213 8 Base 0x08D6 0x08FF Reserved B...

Page 213: ...s 32 bits Figure 6 2 shows the MCU ID register values Address Base 0x0004 Access R O 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R PARTNUM W MPC5566 part number 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 16 17 18 19 2...

Page 214: ...Simultaneous reset requests are prioritized When reset requests with different priorities occur on the same clock cycle the reset request with the highest priority is serviced and the status bit of on...

Page 215: ...PORS Power on reset status 0 Another reset source was acknowledged by the reset controller since the last assertion of the power on reset input 1 The power on reset input to the reset controller was a...

Page 216: ...7 28 Reserved 29 30 BOOTCFG Reset configuration pin status BOOTCFG 0 1 identifies the address of the reset configuration halfword RCHW and whether arbitration is used by the boot assist module BAM 00...

Page 217: ...ut no previously set bits in the SIU_RSR are cleared Reason The SERF flag bit is cleared by writing a 1 write 1 to clear to the bit location or when another reset source is asserted Case 3 Condition L...

Page 218: ...y other reset source asserts 0 No software system reset 1 Generate an software internal system reset 1 SER Software external reset Used to generate a software external reset Writing a 1 to this bit as...

Page 219: ...26 27 28 29 30 31 R EIF15 EIF14 EIF13 EIF12 EIF11 EIF10 EIF9 EIF8 EIF7 EIF6 EIF5 EIF4 EIF3 EIF2 EIF1 EIF0 W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0...

Page 220: ...15 Reserved 16 31 EIREn External interrupt request enable n Enables the assertion of the interrupt request from the SIU to the interrupt controller when an edge triggered event occurs on the IRQ n pin...

Page 221: ...0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R OVF 15 OVF 14 OVF 13 OVF 12 OVF 11 OVF 10 OVF 9 OVF 8 OVF 7 OVF 6 OVF 5 OVF 4 OVF 3 OVF 2 OVF...

Page 222: ...0x0024 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R ORE 15 ORE 14 ORE 13...

Page 223: ...0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R IREE 15 IREE 14 IREE 13 IREE 12 IREE 11 IREE 10 IREE 9 IREE 8 IREE 7 IREE 6 IREE 5 IREE 4 IREE 3 IREE 2 IREE 1 IREE 0 W Reset 0 0 0 0 0...

Page 224: ...ling edge event enable n Enables falling edge triggered events on the corresponding IRQ n pin 0 Falling edge event is disabled 1 Falling edge event is enabled Address Base 0x0030 Access R W 0 1 2 3 4...

Page 225: ...All device pin names begin with the primary function followed by the alternate function and then GPIO In some cases the third function can be a secondary alternate which supersedes the GPIO Those exc...

Page 226: ...O pad type 00 10 pF drive strength 01 20 pF drive strength 10 30 pF drive strength 11 50 pF drive strength 10 ODE Open drain output enable Controls output driver configuration for the pads Either open...

Page 227: ...l device for the pad 15 WPS Weak pullup down select Controls whether weak pullup or weak pulldown devices are used for the pad when weak pullup down devices are enabled The WKPCFG pin determines wheth...

Page 228: ...2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA1 1 Do not configure the PA fields in PCR1 3 and PCR5 7 to select ADDR 9 11 Configure only one set of pins to ADDR 9 11 for the address input OBE2 2 When...

Page 229: ...1 IBE3 3 When configured as ADDR 8 11 or GPDO set the IBE bit to 1 to reflect the pin state in the GPDI register Clear the IBE bit to 0 to reduce power consumption When configured as GPDI set the IBE...

Page 230: ...PA Field Pin Function 0b0 GPIO 8 22 0b1 ADDR 12 26 Address Base 0x006E 0x0072 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 PA OBE1 1 When configured as ADDR 27 29 the OBE bit has no e...

Page 231: ...o reflect the pin state in the corresponding GPDI register Clear the IBE to zero to reduce power consumption When configured as GPDI set the IBE bit to 1 DSC ODE3 3 When configured as ADDR 30 31 or AD...

Page 232: ...IBE2 2 When configured as DATA 16 or FEC_TX_CLK set the IBE bit to 1 to show the pin state in the GPDI register Clear the IBE bit to 0 to reduce power consumption When configured as GPDI set the IBE...

Page 233: ...ak pullup settings when configured as DATA 18 or FEC_TX_ER WPS5 W RESET 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 Address Base 0x009E Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE1 1 When co...

Page 234: ...register Clear the IBE bit to 0 to reduce power consumption When configured as GPDI set the IBE bit to 1 DSC ODE3 3 When configured as DATA 21 or FEC_RX_ER clear the ODE bit to 0 HYS4 4 If external m...

Page 235: ...22 0b10 FEC_RXD 0 0b11 DATA 22 Address Base 0x00A6 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE1 1 When configured as DATA 23 or FEC_TXD 3 the OBE bit has no effect When configur...

Page 236: ...IBE bit to 0 to reduce power consumption When configured as GPDI set the IBE bit to 1 DSC ODE3 3 When configured as DATA 24 or FEC_COL clear the ODE bit to 0 HYS4 4 If external master operation is ena...

Page 237: ...0b10 FEC_RX_DV 0b11 DATA 25 Address Base 0x00AC Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE1 1 When configured as DATA 26 or FEC_TX_EN the OBE bit has no effect When configured...

Page 238: ...r Clear the IBE bit to 0 to reduce power consumption When configured as GPDI set the IBE bit to 1 DSC ODE3 3 When configured as DATA 27 or FEC_TXD 2 clear the ODE bit to 0 HYS4 4 If external master op...

Page 239: ...A 28 0b10 FEC_TXD 1 0b11 DATA 28 Address Base 0x00B2 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE1 1 When configured as DATA 29 or FEC_RXD 1 the OBE bit has no effect When configu...

Page 240: ...er Clear the IBE bit to 0 to reduce power consumption When configured as GPDI set the IBE bit to 1 DSC ODE3 3 When configured as DATA 30 or FEC_RXD 2 clear the ODE bit to 0 HYS4 4 If external master o...

Page 241: ...Function 0b00 GPIO 59 0b01 DATA 31 0b10 FEC_RXD 3 0b11 DATA 31 Address Base 0x00B8 0x00BA Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 PA OBE1 1 When configured as TSIZ 0 1 the OBE bit...

Page 242: ...bit to 1 to show the pin state in the GPDI register Clear the IBE bit to 0 to reduce power consumption When configured as GPDI set the IBE bit to 1 DSC ODE3 3 When configured as RD_WR clear the ODE b...

Page 243: ...Registers SIU_PCR66 SIU_PCR67 Address Base 0x00C0 0x00C2 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 PA OBE1 1 When configured as WE BE 0 1 the OBE bit has no effect When configured a...

Page 244: ...PDO set the OBE bit to 1 IBE2 2 When the pad is configured as an output set the IBE bit to 1 to show the pin state in the GPDI register Clear the IBE bit to 0 to reduce power consumption When configur...

Page 245: ...A_GPIO 71 Table 6 43 PCR69 PA Field Definition PA Field Pin Function 0b0 GPIO 69 0b1 TS Address Base 0x00CC Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 PA OBE1 1 When configured as TA...

Page 246: ...configured as TEA the OBE bit has no effect When configured as GPDO set the OBE bit to 1 IBE2 2 When the pad is configured as an output set the IBE bit to 1 to show the pin state in the GPDI register...

Page 247: ...set the OBE bit to 1 IBE2 2 When the pad is configured as an output set the IBE bit to 1 to show the pin state in the GPDI register Clear the IBE bit to 0 to reduce power consumption When configured a...

Page 248: ...PCR83 The SIU_PCR83 register controls the function direction and electrical attributes of CNTXA_TXDA_GPIO 83 Figure 6 50 CNTXA_TXDA_GPIO 83 Pad Configuration Register SIU_PCR83 Table 6 48 PCR74 PA Fie...

Page 249: ...n 0b00 GPIO 83 0b01 CNTXA 0b10 TXDA 0b11 CNTXA Address Base 0x00E8 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE1 1 When configured as CNRXA or RXDA the OBE bit has no effect When...

Page 250: ...nitions Table 6 52 lists the PA fields for CNRXB_PCSC 4 _GPIO 86 Table 6 51 PCR85 PA Field Definitions PA Field Pin Function 0b00 GPIO 85 0b01 CNTXB 0b10 PCSC 3 0b11 CNTXB Address Base 0x00EC Access R...

Page 251: ...hen configured as CNTXC or PCSD 3 the OBE bit has no effect When configured as GPDO set the OBE bit to 1 IBE2 2 When the pad is configured as an output set the IBE bit to 1 to show the pin state in th...

Page 252: ...Address Base 0x00F2 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 PA OBE1 1 When configured as TXDA the OBE bit has no effect When configured as GPDO set the OBE bit to 1 IBE2 2 When th...

Page 253: ...F6 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE1 1 When configured as TXDB or PCSD 1 the OBE bit has no effect When configured as GPDO set the OBE bit to 1 IBE2 2 When the pad is...

Page 254: ...ld Definitions PA Field Pin Function 0b00 GPIO 92 0b01 RXDB 0b10 PCSD 5 0b11 RXDB Address Base 0x00FA Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA1 1 The SCKA function is available on...

Page 255: ...0 0 0 PA1 1 The SINA function is available on the MPC5566 only OBE2 2 When configured as SINA or PCSC 2 the OBE bit has no effect When configured as GPDO set the OBE bit to 1 IBE3 3 When the pad is co...

Page 256: ...ield Pin Function 0b00 GPIO 95 0b01 SOUTA 0b10 PCSC 5 0b11 SOUTA Address Base 0x0100 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA1 1 The PCSA 0 function is available on the MPC5566 on...

Page 257: ...0 0 PA1 1 The PCSA 1 function is available on the MPC5566 only OBE2 2 When configured as PCSA 1 or PCSB 2 the OBE bit has no effect When configured as GPDO set the OBE bit to 1 IBE3 3 When the pad is...

Page 258: ...ions Table 6 65 lists the PA fields for PCSA 3 _SIND_GPIO 99 Table 6 64 PCR98 PA Field Definitions PA Field Pin Function 0b00 GPIO 98 0b01 PCSA 2 0b10 SCKD 0b11 PCSA 2 Address Base 0x0106 Access R W 0...

Page 259: ...is available on the MPC5566 only OBE2 2 When configured as PCSA 4 or SOUTD the OBE bit has no effect When configured as GPDO set the OBE to 1 IBE3 3 When PCSA 4 or SOUTD is configured for slave opera...

Page 260: ...lds for SCKB_PCSC 1 _GPIO 102 Table 6 67 PCR101 PA Field Definitions PA Field Pin Function 0b00 GPIO 101 0b01 PCSA 5 0b10 PCSB 3 0b11 PCSA 5 Address Base 0x010C Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12...

Page 261: ...as SINB clear the OBE bit to 0 When configured as PCSC 2 the OBE bit has no effect When configured as GPDO set the OBE bit to 1 IBE2 2 When the pad is configured as an output set the IBE bit to 1 to...

Page 262: ...Pin Function 0b00 GPIO 104 0b01 SOUTB 0b10 PCSC 5 0b11 SOUTB Address Base 0x0112 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE1 1 When configured as PCSB 0 set the OBE bit to 1 fo...

Page 263: ...ear to 0 for slave operation When configured as PCSB 1 the OBE bit has no effect When configured as GPDO set the OBE bit to 1 IBE2 2 When configured as PCSD 0 in slave operation set the IBE bit to 1 W...

Page 264: ...ds for PCSB 3 _SINC_GPIO 108 Table 6 73 PCR107 PA Field Definitions PA Field Pin Function 0b00 GPIO 107 0b01 PCSB 2 0b10 SOUTC 0b11 PCSB 2 Address Base 0x0118 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 1...

Page 265: ...d as GPDO set the OBE bit to 1 IBE2 2 When the pad is configured as an output set the IBE bit to 1 to show the pin state in the GPDI register Clear the IBE bit to 0 to reduce power consumption When co...

Page 266: ...0b00 GPIO 110 0b01 PCSB 5 0b10 PCSC 0 0b11 PCSB 5 Address Base 0x011E 0x0120 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 PA OBE1 1 When ETRIG 0 1 is configured the OBE has no effect...

Page 267: ...fields for ETPUA 0 3 _ETPUA 12 15 _GPIO 114 117 Table 6 78 PCR113 PA Field Definitions PA Field Pin Function 0b00 GPIO 113 0b01 TCRCLKA 0b10 IRQ 7 0b11 TCRCLKA Address Base 0x0124 0x012A Access R W 0...

Page 268: ...The OBE bit must be set to 1 for ETPUA 4 ETPUA 16 and GPIO 118 when configured as outputs When configured as ETPUA 16 the OBE bit has no effect IBE2 2 The IBE bit must be set to 1 for ETPUA 4 ETPUA 1...

Page 269: ...ETPUA 6 _ETPUA 18 _GPIO 120 Table 6 81 PCR119 PA Field Definitions PA Field Pin Function 0b00 GPIO 119 0b01 ETPUA 5 0b10 ETPUA 17 0b11 ETPUA 5 Address Base 0x0130 Access R W 0 1 2 3 4 5 6 7 8 9 10 11...

Page 270: ...elds for ETPUA 7 _ETPUA 19 _GPIO 121 Address Base 0x0132 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE1 1 The OBE bit must be set to 1 for ETPUA 7 and GPIO 121 when configured as o...

Page 271: ...14 15 R 0 0 0 0 PA OBE1 1 The OBE bit must be set to 1 for ETPUA 8 10 or GPIO 122 124 when configured as outputs When configured as ETPUA 20 the OBE bit has no effect IBE2 2 The IBE bit must be set t...

Page 272: ...Definitions PA Field Pin Function 0b00 GPIO 125 0b01 ETPUA 11 0b10 ETPUA 23 0b11 ETPUA 11 Address Base 0x013C Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE1 1 When configured as PC...

Page 273: ...t must be set to 1 for ETPUA 13 15 or GPIO 127 129 when configured as outputs IBE2 2 The IBE bit must be set to 1 for ETPUA 13 15 PSCB 3 5 or GPIO 127 129 when configured as inputs When configured as...

Page 274: ...PCR133 PA Field Definitions PA Field Pin Function 0b00 GPIO 130 133 0b01 ETPUA 16 19 0b10 PCSD 1 4 0b11 ETPUA 16 19 Address Base 0x014C Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA O...

Page 275: ...as outputs IBE2 2 When the pad is configured as an output setting the IBE bit to 1 allows the pin state to be reflected in the corresponding GPDI register Setting the IBE bit to zero reduces power co...

Page 276: ...PA Field Definitions PA Field Pin Function 0b00 GPIO 136 0b01 ETPUA 22 0b10 IRQ 10 0b11 ETPUA 22 Address Base 0x0152 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA OBE1 1 When configur...

Page 277: ...ETPUA 24 27 or IRQ 12 15 the OBE bit has no effect The OBE bit must be set to 1 for GPIO 138 141 when configured as output IBE2 2 When the pad is configured as an output set the IBE bit to 1 to show...

Page 278: ...tributes of TCRCLKB_IRQ 6 _GPIO 146 Table 6 94 PCR142 PCR144 PA Field Definitions PA Field Pin Function 0b00 GPIO 142 144 0b01 ETPUA 28 30 0b10 PCSC 1 3 0b11 ETPUA 28 30 Address Base 0x0162 Access R W...

Page 279: ...d as GPDO set the OBE bit to 1 IBE2 2 When the pad is configured as an output set the IBE bit to 1 to show the pin state in the GPDI register Clear the IBE bit to 0 to reduce power consumption When co...

Page 280: ...R147 PCR162 PA Field Definitions PA Field Pin Function 0b00 GPIO 147 162 0b01 ETPUB 0 15 0b10 ETPUB 16 31 0b11 ETPUB 0 15 Address Base 0x0186 0x018C Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R...

Page 281: ...13 14 15 R 0 0 0 0 0 PA OBE1 1 The OBE bit must be set to one for ETPUB 20 31 or GPIO 167 178 when configured as outputs IBE2 2 When the pad is configured as an output set the IBE bit to 1 to show th...

Page 282: ...IOS 10 11 _PCSD 3 4 _GPIO 189 190 Table 6 100 PCR179 PCR188 PA Field Definitions PA Field Pin Function 0b00 GPIO 179 188 0b01 EMIOS 0 9 0b10 ETPUA 0 9 0b11 EMIOS 0 9 Address Base 0x01BA 0x01BC Access...

Page 283: ...O 191 when configured as an output IBE2 2 When the pad is configured as an output set the IBE bit to 1 to show the pin state in the GPDI register Clear the IBE bit to 0 to reduce power consumption The...

Page 284: ...S 14 _IRQ 0 _CNTXD_GPIO 193 Table 6 103 PCR192 PA Field Definitions PA Field Pin Function 0b00 GPIO 192 0b01 EMIOS 13 0b10 SOUTD 0b11 EMIOS 13 Address Base 0x01C2 Access R W 0 1 2 3 4 5 6 7 8 9 10 11...

Page 285: ...The OBE bit must be set to 1 for GPIO 194 when configured as output IBE2 2 When the pad is configured as an output set the IBE bit to 1 to show the pin state in the GPDI register Clear the IBE bit to...

Page 286: ...lds for EMIOS 17 _ETPUB 1 _GPIO 196 Table 6 106 PCR195 PA Field Definitions PA Field Pin Function 0b00 GPIO 195 0b01 EMIOS 16 0b10 ETPUB 0 0b11 EMIOS 16 Address Base 0x01C8 Access R W 0 1 2 3 4 5 6 7...

Page 287: ...14 15 R 0 0 0 0 PA OBE1 1 The OBE bit must be set to 1 for EMIOS 18 or GPIO 197 when configured as output IBE2 2 When the pad is configured as an output set the IBE bit to 1 to show the pin state in t...

Page 288: ...PA fields for EMIOS 20 21 _ETPUB 4 5 _GPIO 199 200 Table 6 109 PCR198 PA Field Definitions PA Field Pin Function 0b00 GPIO 198 0b01 EMIOS 19 0b10 ETPUB 3 0b11 EMIOS 19 Address Base 0x01CE 0x01D0 Acce...

Page 289: ...5 R 0 0 0 0 PA OBE1 1 The OBE bit must be set to 1 for EMIOS 22 or GPIO 201 when configured as output IBE2 2 When the pad is configured as an output set the IBE bit to 1 to show the pin state in the G...

Page 290: ...lists the PA fields for EMIOS 14 15 _GPIO 203 204 6 3 1 114 Pad Configuration Register 205 SIU_PCR205 The SIU_PCR205 register controls the direction and electrical attributes of the GPIO 205 pin This...

Page 291: ...then select the GPIO ADC trigger in the SIU_ETISR register The input source for each SIN SS SCK and trigger signal is individually specified in the DSPI input select register SIU_DISR Refer to Section...

Page 292: ...t has no effect When configured as GPDO set the OBE bit to 1 IBE3 3 When the pad is configured as an output set the IBE bit to 1 to show the pin state in the GPDI register Clear the IBE bit to 0 to re...

Page 293: ...the PA fields for RSTCFG_GPIO 210 Table 6 115 PCR209 PA Field Definitions PA Field Pin Function 0b000 GPIO 209 0b001 PLLCFG 1 0b010 IRQ 5 0b011 PLLCFG 1 0b100 SOUTD Address Base 0x01E4 Access R W 0 1...

Page 294: ...during reset Set the PA field to 0b10 for IRQ 2 3 or to 0b00 for GPIO 211 212 OBE2 2 When configured as IRQ 2 3 the OBE bit has no effect When configured as GPDO set the OBE bit to 1 IBE3 3 When the...

Page 295: ...er to Table 6 19 for bit field definitions Table 6 119 lists the PA fields for AN 12 _MA 0 _SDS Table 6 118 PCR213 PA Field Definitions PA Field Pin Function 0b0 GPIO 0b1 WKPCFG Address Base 0x01EC Ac...

Page 296: ...fers are enabled disabled based on PA selection Both input and output buffers are disabled for AN 13 function Output buffers only can be enabled for MA 1 and SDO functions 2 To select the SDO function...

Page 297: ...strength of MDO 3 0 Figure 6 128 MDO 3 0 Pad Configuration Register SIU_PCR223 SIU_PCR220 Address Base 0x01F4 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PA1 2 1 Input and output buffer...

Page 298: ...ure 6 131 EVTO Pad Configuration Register SIU_PCR227 6 3 1 131 Pad Configuration Register 228 SIU_PCR228 The SIU_PCR228 register controls the drive strength of TDO Figure 6 132 TDO Pad Configuration R...

Page 299: ...sters are not implemented in this device 6 3 1 135 Pad Configuration Register 256 SIU_PCR256 The SIU_PCR256 register controls the function direction and electrical attributes of CAL_CS 0 Figure 6 135...

Page 300: ...finitions Table 6 125 lists the PA fields for CAL_ADDR 12 6 3 1 138 Pad Configuration Register 260 SIU_PCR260 The SIU_PCR260 register controls the function direction and electrical attributes of CAL_A...

Page 301: ...attributes of CAL_ADDR 14 Figure 6 139 CAL_ADDR 14 Pad Configuration Register SIU_PCR261 Refer to Table 6 19 for bit field definitions Table 6 127 lists the PA fields for CAL_ADDR 14 Table 6 126 PCR2...

Page 302: ...129 lists the PA fields for CAL_ADDR 16 6 3 1 142 Pad Configuration Register 264 SIU_PCR264 The SIU_PCR264 register controls the function direction and electrical attributes of CAL_ADDR 17 Figure 6 14...

Page 303: ...function direction and electrical attributes of CAL_ADDR 19 Figure 6 144 CAL_ADDR 19 Pad Configuration Register SIU_PCR266 Refer to Table 6 19 for bit field definitions Table 6 132 lists the PA field...

Page 304: ...134 lists the PA fields for CAL_ADDR 21 6 3 1 147 Pad Configuration Register 269 SIU_PCR269 The SIU_PCR269 register controls the function direction and electrical attributes of CAL_ADDR 22 Figure 6 1...

Page 305: ...ntrols the function direction and electrical attributes of CAL_ADDR 25 27 Figure 6 149 CAL_ADDR 25 27 Pad Configuration Registers SIU_PCR272 SIU_PCR274 Refer to Table 6 19 for bit field definitions Ta...

Page 306: ...139 lists the PA fields for CAL_ADDR 29 6 3 1 152 Pad Configuration Register 277 SIU_PCR277 The SIU_PCR277 register controls the function direction and electrical attributes of CAL_ADDR 30 Figure 6 1...

Page 307: ...trols the function direction and electrical attributes of the CAL_RD_WR Figure 6 154 CAL_RD_WR Pad Configuration Registers SIU_PCR294 Refer to Table 6 19 for bit field definitions Table 6 142 lists th...

Page 308: ...initions Table 6 144 lists the PA fields for CAL_OE 6 3 1 157 Pad Configuration Register 298 SIU_PCR298 The SIU_PCR298 register controls the function direction and electrical attributes of CAL_TS Figu...

Page 309: ...ample SIU_GPDO0 contains the PDO0 bit for CS 0 _GPIO 0 and SIU_GPDO213 contains the PDO213 bit for WKPCFG_GPIO 213 The address for a GPDO pin is the GPIO number plus an offset of SIU_BASE 0x0600 Softw...

Page 310: ...are not implemented in the package Software reads the SIU_GPDIn registers to get the input state of the external GPIO pin Each GPDI register contains the input state of one external GPIO pin If a GPD...

Page 311: ...he timer output pin must change to the state that the eQADC recognizes as a trigger Rising or falling edges and low or high gated triggers are all valid events that activate a trigger therefore it is...

Page 312: ...e 6 150 SIU_ETISR Field Descriptions Bits Name Description 0 1 TSEL5 0 1 eQADC trigger input select 5 Specifies the input for eQADC trigger 5 00 GPIO 207 01 ETPUA 26 channel 10 EMIOS 12 channel 11 ETR...

Page 313: ...29 30 31 R ESEL7 ESEL6 ESEL5 ESEL4 ESEL3 ESEL2 ESEL1 ESEL0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6 162 External IRQ Input Select Register SIU_EIISR Table 6 151 SIU_EIISR Field Descriptions B...

Page 314: ...11 PCSD 11 serialized input ETPUA 28 14 15 ESEL8 0 1 External IRQ input select 8 Specifies the input for IRQ 8 00 IRQ 8 01 PCSB 8 serialized input ETPUA 29 10 PCSC 9 serialized input ETPUA 5 11 PCSD 1...

Page 315: ...nput ETPUA 21 10 PCSC 3 serialized input ETPUA 15 11 PCSD 4 serialized input ETPUA 17 28 29 ESEL1 0 1 External IRQ input select 1 Specifies the input for IRQ 1 00 IRQ 1 01 PCSB 1 serialized input EMIO...

Page 316: ...IO 93 pin 01 SCKB master 10 SCKC master 11 SCKD master 6 7 TRIGSELA 0 1 DSPI A trigger input select Specifies the source of the DSPI A trigger input 00 No Trigger 01 PCSB 4 10 PCSC 4 11 PCSD 4 8 9 SIN...

Page 317: ...elect Specifies the source of the DSPI C trigger input for master or slave mode 00 Invalid value 01 PCSA 4 10 PCSB 4 11 PCSD 4 24 25 SINSELD 0 1 DSPI D data input select Specifies the source of the DS...

Page 318: ...2 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSRE TEST W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 6 153 SIU_CCR Field Descriptions Bits Name Description 0 13 Reserved 14 MATCH Compare...

Page 319: ...the non calibration bus pins that have a negated state to which the pins return at the end of an access Those reflections always are suppressed Furthermore the suppression of reflections from the non...

Page 320: ...he following equation The maximum ENGCLK frequency is 72 MHz 144 MHz 2 Note Clearing ENGDIV to 0 is the reset setting Synchronization between ENGCLK and CLKOUT cannot be guaranteed when ENGDIV is 0 24...

Page 321: ...U_CBRL register The CMPAL field is read write and is reset by the synchronous reset signal Address Base 0x0988 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CMPAH W Reset 0 0 0 0 0 0 0 0 0 0 0 0...

Page 322: ...ignal 6 4 Functional Description The following sections provide a functional overview of the SIU operation 6 4 1 System Configuration The following sections describe the system configuration Address B...

Page 323: ...and the boot mode defaults to Boot from internal flash memory Refer to Section 16 3 2 2 5 Read the Reset Configuration Halfword for details on the RCHW 6 4 1 2 Pad Configuration The pad configuration...

Page 324: ...erts for 10 clock cycles The reset controller does not respond to assertions of the RESET pin if a reset cycle is already being processed 6 4 3 External Interrupt There are 1516 external interrupt inp...

Page 325: ...ration register PCR in the SIU where the GPIO function is selected In addition each device GPIO signal has an input data register SIU_GPDIn and an output data register SIU_GPDOn 6 4 5 Internal Multipl...

Page 326: ...e of the following pins External pin eTPU channel eMIOS channel The input source for each eQADC external trigger is configured in the eQADC trigger input select register SIU_ETISR As shown in the figu...

Page 327: ...output signal The remaining IRQ inputs are multiplexed in the same manner The inputs to the IRQ from each DSPI module are offset by one so that if more than one DSPI module is connected to the same ex...

Page 328: ...inputs through the slaves with the last slave MTRIG output connected to the master trigger input An example of a serial chain is shown in Figure 6 174 Parallel chaining allows the PCS and SCK from on...

Page 329: ...ocontroller Reference Manual Rev 2 6 126 Freescale Semiconductor Figure 6 174 DSPI Serial Chaining SOUT SOUT SIN SIN PCS 0 SS SCK SCK IN SS SCK IN SIN SOUT External SPI device MTRIG Trigger SOUTB SCKA...

Page 330: ...er Reference Manual Rev 2 Freescale Semiconductor 6 127 Figure 6 175 DSPI Parallel Chaining SOUT SOUT SIN SIN PCS 0 SS SCK SCK IN SS SCK IN SIN SOUT External SPI device SIN SCK IN SS SOUT External SPI...

Page 331: ...System Integration Unit SIU MPC5566 Microcontroller Reference Manual Rev 2 6 128 Freescale Semiconductor...

Page 332: ...am Figure 7 1 shows a block diagram of the crossbar switch Figure 7 1 XBAR Block Diagram Table 7 1 gives the crossbar switch port for each master and slave and the assigned and fixed ID number for eac...

Page 333: ...are granted access to a slave port in round robin fashion based upon the ID of the last master to be granted access A block diagram of the XBAR is shown in Figure 7 1 The XBAR can place a slave port i...

Page 334: ...rpose control register for slave port 0 32 Base 0x0014 0x00FF Reserved Base 0x0100 XBAR_MPR1 Master priority register for slave port 1 32 Base 0x0104 0x010F Reserved Base 0x0110 XBAR_SGPCR1 General pu...

Page 335: ...er port when operating in fixed priority mode They are ignored in round robin priority mode unless more than one master has been assigned high priority by a slave NOTE Masters must be assigned unique...

Page 336: ...Set the arbitration priority for master port 3 on the associated slave port 000 This master has the highest priority when accessing the slave port 100 This master has the lowest priority when accessin...

Page 337: ...ll power savings if the slave port is not saturated however an extra clock of latency results whenever any master tries to access a slave not being accessed by another master because it is not parked...

Page 338: ...ave port s registers can be written 1 All this slave port s registers are read only and cannot be written attempted writes have no effect and result in an error response 1 21 Reserved must be cleared...

Page 339: ...ing master receives wait states until the targeted slave port can service the master request The latency in servicing the request depends on each master s priority level and the responding slave s acc...

Page 340: ...the XBAR is completely transparent and the master access is immediately transmitted on the slave bus and no arbitration delays are incurred A master access stall if the access decodes to a slave port...

Page 341: ...that the proper master if any has control of the slave port If the new requesting master s priority level is higher than that of the master that currently has control of the slave port the higher pri...

Page 342: ...uesting master must wait until the end of the fixed length burst transfer before it is granted control of the slave port If the new requesting master s priority level is lower than that of the master...

Page 343: ...Crossbar Switch XBAR MPC5566 Microcontroller Reference Manual Rev 2 7 12 Freescale Semiconductor...

Page 344: ...t doubleword In this case it is corrected automatically by hardware and no flags or other indicators are set by the error that occurred A non correctable ECC error is generated when two bits in a 64 b...

Page 345: ...Base 0x001F ECSM_SWTIR Software watchdog timer interrupt register 1 8 Base 0x0020 0x0023 Reserved Base 0x0024 0x0027 FBOMCR FEC Burst Optimization Master Control Register 32 Base 0x0028 0x0042 Reserv...

Page 346: ...he device The e200z6 core also provides this functionality and is the preferred method for watchdog implementation To optimize code portability to other Power Architecture based products in the MPC550...

Page 347: ...C_IRQ ECSM_ECR ERNCR ECSM_ESR RNCE ram noncorrectable error ECSM_ECR EFNCR ECSM_ESR FNCE flash noncorrectable error where the combination of the following criteria generates the interrupt request Corr...

Page 348: ...AM non correctable error RNCE events before flash non correctable error FNCE events 8 2 1 5 ECC Error Generation Register ECSM_EEGR The ECSM_EEGR is a 16 bit control register used to generate double b...

Page 349: ...are continuously generated The assertion of this bit forces the internal SRAM controller to create 2 bit data errors as defined by the bit position specified in ERRBIT 0 6 and the overall odd parity b...

Page 350: ...specified by this field plus the odd parity bit of the ECC code are inverted The internal SRAM controller follows a vector bit ordering scheme where LSB 0 Errors in the ECC syndrome bits can be gener...

Page 351: ...ed ECC event in the flash memory Depending on the state of the ECSM_ECR register an ECC event in the flash loads the address attributes and data of the access into the ECSM_FEAR ECSM_FEMR ECSM_FEAT an...

Page 352: ...gnifies a bit that is uninitialized Figure 8 6 Flash ECC Attributes Register ECSM_FEAT Table 8 7 ECSM_FEAT Field Descriptions Field Description 0 WRITE Write The reset value of this field is undefined...

Page 353: ...ECSM_FEAR ECSM_FEMR ECSM_FEAT and ECSM_FEDR registers and asserts the FNCE flag in ECSM_ESR Base 0x0058 Access Read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R FEDH W Reset 1 U U U U U U U U U U U U U U U...

Page 354: ...L W Reset 1 U U U U U U U U U U U U U U U U 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R FEDL W Reset 1 U U U U U U U U U U U U U U U U 1 U signifies a bit that is uninitialized Figure 8 8 Flash...

Page 355: ...in the RAM memory Depending on the state of the ECSM_ECR an ECC event in the RAM loads the address attributes and data of the access into the ECSM_REAR ECSM_REMR ECSM_REAT and ECSM_REDR registers and...

Page 356: ...1 U signifies a bit that is uninitialized Figure 8 11 RAM ECC Attributes Register ECSM_REAT Table 8 12 ECSM_REAT Field Descriptions Field Description 0 WRITE Write The reset value of this field is und...

Page 357: ...EAT ECSM_REDRH ECSM_REDRL and asserts the RFNCE flag in ECSM_ESR The data captured on a multi bit non correctable ECC error is undefined Base 0x0068 Access Read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R...

Page 358: ...he ECC uses the check bits to automatically correct single bit memory errors Multi bit memory errors are not correctable If the ECC detects a multi bit error an exception is generated The type of exce...

Page 359: ...memory and SRAM To enable non correctable error reporting and save the error details for SRAM set the ERNCR bit in the ECSM Error Configuration Register ECSM_ECR Flash set the EFNCR bit in ECSM_ECR W...

Page 360: ...Ensure that the INTC_PSR PRI value for the ECC error interrupt request is 0 To use the detailed data or instruction storage exception information design an exception handler that can determine The des...

Page 361: ...Error Correction Status Module ECSM MPC5566 Microcontroller Reference Manual Rev 2 8 18 Freescale Semiconductor...

Page 362: ...ncludes a DMA engine which performs source and destination address calculations and the actual data movement operations along with SRAM based local memory containing the transfer control descriptors T...

Page 363: ...tatically known and is not defined within the data packet itself The eDMA module features All data movement via dual address transfers read from source write to destination Programmable source destina...

Page 364: ...r channel optionally asserted at completion of major iteration count Error terminations are enabled per channel and logically summed together to form two error interrupts Support for scatter gather DM...

Page 365: ...eDMA enable error interrupt low register 32 Base 0x0018 EDMA_SERQR eDMA set enable request register 8 Base 0x0019 EDMA_CERQR eDMA clear enable request register 8 Base 0x001A EDMA_SEEIR eDMA set enabl...

Page 366: ...rity register 8 Base 0x0114 EDMA_CPR20 eDMA channel 20 priority register 8 Base 0x0115 EDMA_CPR21 eDMA channel 21 priority register 8 Base 0x0116 EDMA_CPR22 eDMA channel 22 priority register 8 Base 0x...

Page 367: ...R52 eDMA channel 52 priority register 8 Base 0x0135 EDMA_CPR53 eDMA channel 53 priority register 8 Base 0x0136 EDMA_CPR54 eDMA channel 54 priority register 8 Base 0x0137 EDMA_CPR55 eDMA channel 55 pri...

Page 368: ...trol descriptor 20 256 Base 0x12A0 TCD21 eDMA transfer control descriptor 21 256 Base 0x12C0 TCD22 eDMA transfer control descriptor 22 256 Base 0x12E0 TCD23 eDMA transfer control descriptor 23 256 Bas...

Page 369: ...15A0 TCD45 eDMA transfer control descriptor 45 256 Base 0x15C0 TCD46 eDMA transfer control descriptor 46 256 Base 0x15E0 TCD47 eDMA transfer control descriptor 47 256 Base 0x1600 TCD48 eDMA transfer c...

Page 370: ...rst where priority level 3 is the highest and priority level 0 is the lowest The group priorities are assigned in the GRPnPRI fields of the eDMA control register EDMA_CR All group priorities must have...

Page 371: ...loop channel linking is enabled upon channel completion a configuration error is reported when the link is attempted if the TCD CITER E_LINK bit does not equal the TCD BITER E_LINK bit All configurat...

Page 372: ...icing the next appropriate channel A channel that experiences an error condition is not automatically disabled If a channel is terminated by an error and then issues another service request before the...

Page 373: ...F field indicating TCD SOFF is inconsistent with TCD SSIZE 26 DAE Destination address error 0 No destination address configuration error 1 The last recorded error was a configuration error detected in...

Page 374: ...11 12 13 14 15 R ERQ 63 ERQ 62 ERQ 61 ERQ 60 ERQ 59 ERQ 58 ERQ 57 ERQ 56 ERQ 55 ERQ 54 ERQ 53 ERQ 52 ERQ 51 ERQ 50 ERQ 49 ERQ 48 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25...

Page 375: ...nd this error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted Address Base 0x0010 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15...

Page 376: ...rresponding bit in the EDMA_ERQRH or EDMA_ERQRL to be cleared Setting bit 1 CERQn provides a global clear function forcing the entire contents of the EDMA_ERQRH and EDMA_ERQRL to be zeroed disabling a...

Page 377: ...write causes the corresponding bit in the EDMA_EEIRH or EDMA_EEIRL to be cleared Setting bit 1 CEEIn provides a global clear function forcing the entire contents of the EDMA_EEIRH or EDMA_EEIRL to be...

Page 378: ...EDMA_ERH or EDMA_ERL to disable the error condition flag for a given channel The given value on a register write causes the corresponding bit in the EDMA_ERH or EDMA_ERL to be cleared Setting bit 1 CE...

Page 379: ...write causes the DONE bit in the corresponding transfer control descriptor to be cleared Setting bit 1 CDSBn provides a global clear function forcing all DONE bits to be cleared Address Base 0x001D Ac...

Page 380: ...ing the interrupt request Typically a write to the EDMA_CIRQR in the interrupt service routine is used for this purpose The state of any given channel s interrupt request is directly affected by write...

Page 381: ...ddress Base 0x0020 Access User R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R INT 63 INT 62 INT 61 INT 60 INT 59 INT 58 INT 57 INT 56 INT 55 INT 54 INT 53 INT 52 INT 51 INT 50 INT 49 INT 48 W Reset 0 0 0...

Page 382: ...channel can easily be cleared Address Base 0x0028 Access User R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R ERR 63 ERR 62 ERR 61 ERR 60 ERR 59 ERR 58 ERR 57 ERR 56 ERR 55 ERR 54 ERR 53 ERR 52 ERR 51 ER...

Page 383: ...5 26 27 28 29 30 31 R HRS 47 HRS 46 HRS 45 HRS 44 HRS 43 HRS 42 HRS 41 HRS 40 HRS 39 HRS 38 HRS 37 HRS 36 HRS 35 HRS 34 HRS 33 HRS 32 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address Base 0x0034 Access...

Page 384: ...annel s data transfers to be temporarily suspended in favor of starting a higher priority channel After the preempting channel has completed all of its minor loop data transfers the preempted channel...

Page 385: ...hannel n current group priority Group priority assigned to this channel group when fixed priority arbitration is enabled These two bits are read only writes are ignored The reset value for the group p...

Page 386: ...or Link channel number CITER or CITER LINKCH 0x1000 32 x n 167 9 Current major iteration count CITER 0x1000 32 x n 176 16 Destination address offset signed DOFF 0x1000 32 x n 192 32 Last destination a...

Page 387: ...25 26 27 28 29 30 31 0x0000 SADDR 0x0004 SMOD SSIZE DMOD DSIZE SOFF 0x0008 NBYTES 0x000C SLAST 0x0010 DADDR 0x0014 CITER E_ LINK CITER1 or CITER LINKCH 1 If channel linking on minor link completion i...

Page 388: ...dulo size range 37 39 0x4 5 7 SSIZE 0 2 Source data transfer size 000 8 bit 001 16 bit 010 32 bit 011 64 bit 100 Reserved 64 bit 101 32 byte burst 64 bit x 4 110 Reserved 111 Reserved The attempted sp...

Page 389: ...ration count or link channel number If channel to channel linking is disabled TCD CITER E_LINK 0 then No channel to channel linking or chaining is performed after the inner minor loop is exhausted TCD...

Page 390: ...of the MAJOR E_LINK channel linking 0 The channel to channel linking is disabled 1 The channel to channel linking is enabled Note When the TCD is first loaded by software this field must be set equal...

Page 391: ...ed by the eDMA engine not when the first data transfer occurs Note This bit must be cleared to write the MAJOR E_LINK or E_SG bits 249 0x1C 25 ACTIVE Channel active This flag signals the channel is cu...

Page 392: ...ong schemes or where the processor needs an early indication of the data transfer s progress during data movement CITER BITER 1 with INT_HALF enabled generates an interrupt as it satisfies the equatio...

Page 393: ...er address path channel x y After the inner minor loop completes execution the address path hardware writes the new values for the TCDn SADDR DADDR CITER back into the local memory If the major iterat...

Page 394: ...he local TCD memory are included in this module Memory array The TCD is implemented using a single ported synchronous compiled RAM memory array 9 3 2 eDMA Basic Data Flow The basic flow of a data tran...

Page 395: ...s temporarily stored in the data path module until it is gated onto the system bus during the destination write This source read destination write processing continues until the inner minor byte count...

Page 396: ...e final address adjustments and reloading of the BITER field into the CITER Additionally assertion of an optional interrupt request occurs at this time as does a possible fetch of a new TCD from memor...

Page 397: ...nvironment the speed of the source and destination address spaces remains important but the microarchitecture of the eDMA also factors significantly into the resulting metric The peak transfer rates f...

Page 398: ...n the eDMA module and qualified TCD START bit initiated requests start at this point with the registering of the slave write to TCD bit 255 Cycle 3 Channel arbitration begins Cycle 4 Channel arbitrati...

Page 399: ...ts are checked and processed if enabled Cycle n 3 The appropriate fields in the first part of the TCDn are written back into the local memory Cycle n 4 The fields in the second part of the TCDn are wr...

Page 400: ...n the system bus from a cold start no channel is executing eDMA is idle are the following 11 cycles for a software TCD START bit request 12 cycles for a hardware eDMA peripheral request signal request...

Page 401: ...DDR and TCD CITER are written back to the main TCD memory and any minor loop channel linking is performed if enabled If the major loop is exhausted further post processing is executed for example inte...

Page 402: ...rror or EDMA_ESR GPE and EDMA_ESR CPE respectively DMA Request Minor Loop 3 Current Major Loop Iteration Count CITER Example Memory Array DMA Request Minor Loop 2 DMA Request Minor Loop 1 Major Loop x...

Page 403: ...equesting service via the eDMA peripheral request signal If interrupts are enabled for all channels an error interrupt is generated However the channel number for the EDMA_ER and the error interrupt r...

Page 404: ...request of the Receive Data Register Full and LIN Receive Data Ready DMA requests eMIOS_GFR_F0 20 EMIOS GFR F0 eMIOS channel 0 Flag eMIOS_GFR_F1 21 EMIOS GFR F1 eMIOS channel 1 Flag eMIOS_GFR_F2 22 E...

Page 405: ...EIF1 SIU External Interrupt Flag 1 SIU_EISR_EIF2 50 SIU SIU_EISR EIF2 SIU External Interrupt Flag 2 SIU_EISR_EIF3 51 SIU SIU_EISR EIF3 SIU External Interrupt Flag 3 eTPU_CDTRSR_B_DTRS0 52 ETPU CDTRSR_...

Page 406: ...icing the highest priority channel in the next group in the sequence or just skipping a group if it has no pending requests If a channel requests service at a rate that equals or exceeds the round rob...

Page 407: ...s after the channel service request is acknowledged and the channel is selected to execute After the transfer completes the TCD DONE bit is set and an interrupt is generated if correctly enabled For e...

Page 408: ...eration of the minor loop major loop complete 6 eDMA engine writes TCD SADDR 0x1000 TCD DADDR 0x2000 TCD CITER 1 TCD BITER 7 eDMA engine writes TCD ACTIVE 0 TCD DONE 1 EDMA_IRQRn 1 8 The channel retir...

Page 409: ...0x2010 TCD CITER 1 7 eDMA engine writes TCD ACTIVE 0 8 The channel retires one iteration of the major loop The eDMA goes idle or services the next channel 9 Second hardware eDMA peripheral request re...

Page 410: ...minor loop completion when using software initiated service requests The first method is to read the TCD CITER field and test for a change Another method can be extracted from the following sequence T...

Page 411: ...ion is selected for both group and channel arbitration modes A preempt able situation is one in which a preempt enabled channel is running and a higher priority request becomes active When the eDMA en...

Page 412: ...field uses a 15 bit vector to form the current iteration count The bits associated with the TCD CITER LINKCH field are concatenated onto the CITER value to increase the range of the CITER NOTE After...

Page 413: ...time the eDMA engine is retiring the channel The TCD MAJOR E_LINK is set in the programmer s model but it is unclear whether the link completed before the channel retired Use the following coherency m...

Page 414: ...quests1 n1 Priority arbitrator n1 Highest priority interrupt requests n1 Request selector Lowest vector interrupt request n1 Vector encoder Interrupt vector 9 x 4 bits Interrupt acknowledge register I...

Page 415: ...table for statically scheduled hard real time systems The INTC is optimized for a large number of interrupt requests It is targeted to work with a PowerPC book E processor and automotive powertrain ap...

Page 416: ...number 329 with the greatest hexadecimal address IVPR 0x1480 that is available in the interrupt memory map for this device However this number has no relationship to the total number of interrupts ava...

Page 417: ...share a resource coherent accesses to that resource need to be supported The INTC supports the priority ceiling protocol for coherent accesses By providing a modifiable priority mask the priority lev...

Page 418: ...ware vector mode there is a common interrupt exception handler address which is calculated by hardware as shown in Figure 10 5 The upper half of the interrupt vector prefix register IVPR is added to t...

Page 419: ...the write Those values and sizes written to this register neither update the INTC_EOIR contents nor affect whether the LIFO pops For possible future compatibility write four bytes of all 0s to the IN...

Page 420: ...there are sixteen external pins which can be configured in the SIU as external interrupt request input pins When configured for an external interrupt request function an interrupt on that pin sets an...

Page 421: ...al interrupt request I GPIO 113 G GPIO I O ETPUA 20 _ P eTPU A channel I O IRQ 8 _ A External interrupt request I Up Up GPIO 134 G GPIO I O ETPUA 21 _ P eTPU A channel I O IRQ 9 _ A External interrupt...

Page 422: ...bit in the INTC_MCR is asserted a read of the INTC_IACKR has no side effects 32 Base 0x0014 Reserved Base 0x0018 INTC_EOIR INTC end of interrupt register 32 Base 0x001C Reserved Base 0x0020 INTC_SSCI...

Page 423: ...of the INTC Address Base 0x0000 INTC_MCR Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VTES 0 0...

Page 424: ...instruction is also necessary after accessing the resource but before lowering the PRI field Refer to Section 10 5 5 2 Ensuring Coherency 10 3 1 3 INTC Interrupt Acknowledge Register INTC_IACKR The IN...

Page 425: ...fore insert instructions between the reading of the INTC_IACKR and the setting of MSR EE that consumes at least two processor clock cycles This length of time allows the interrupt request negation to...

Page 426: ...t CLRn is the flag bit Writing a 1 to CLRn clears it Writing a 0 to CLRn has no effect If a 1 is written to a pair SETn and CLRn bits at the same time CLRn is asserted regardless of whether CLRn was a...

Page 427: ...t cross a 32 bit boundary NOTE Do not modify the PRIn field in INTC_PSRn when the IRQ is asserted Table 10 7 INTC_SSCIRn Field Descriptions Field Description 0 5 Reserved must be cleared 6 SETn Set fl...

Page 428: ...Clear flag 0 0x0010 1 INTC_SSCIR1 CLR1 INTC software settable Clear flag 1 0x0020 2 INTC_SSCIR2 CLR2 INTC software settable Clear flag 2 0x0030 3 INTC_SSCIR3 CLR3 INTC software settable Clear flag 3 0...

Page 429: ...T21 eDMA channel interrupt 21 0x0210 33 EDMA_IRQRL INT22 eDMA channel interrupt 22 0x0220 34 EDMA_IRQRL INT23 eDMA channel interrupt 23 0x0230 35 EDMA_IRQRL INT24 eDMA channel interrupt 24 0x0240 36 E...

Page 430: ...hannel 10 flag 0x03E0 62 EMIOS_GFR F11 eMIOS channel 11 flag 0x03F0 63 EMIOS_GFR F12 eMIOS channel 12 flag 0x0400 64 EMIOS_GFR F13 eMIOS channel 13 flag 0x0410 65 EMIOS_GFR F14 eMIOS channel 14 flag 0...

Page 431: ...gine A channel 20 interrupt status 0x0590 89 ETPU_CISR_A CIS21 eTPU engine A channel 21 interrupt status 0x05A0 90 ETPU_CISR_A CIS22 eTPU engine A channel 22 interrupt status 0x05B0 91 ETPU_CISR_A CIS...

Page 432: ...ADC receive FIFO 2 drain flag 0x0740 116 EQADC_FISR3 NCF eQADC command FIFO 3 non coherency flag 0x0750 117 EQADC_FISR3 PF eQADC command FIFO 3 pause flag 0x0760 118 EQADC_FISR3 EOQF eQADC command FIF...

Page 433: ...uests Transmit FIFO underflow Receive FIFO overflow 0x0890 137 DSPI_CSR EOQF DSPI C transmit FIFO end of queue flag 0x08A0 138 DSPI_CSR TFFF DSPI C transmit FIFO fill flag 0x08B0 139 DSPI_CSR TCF DSPI...

Page 434: ...or Frame complete interrupts requests Receive register overflow 0x0930 0x0940 147 148 Reserved 0x0950 149 ESCIB_SR TDRE ESCIB_SR TC ESCIB_SR RDRF ESCIB_SR IDLE ESCIB_SR OR ESCIB_SR NF ESCIB_SR FE ESCI...

Page 435: ...FlexCAN A buffer 9 interrupt 0x0A50 165 CANA_IFRL BUF10 FlexCAN A buffer 10 interrupt 0x0A60 166 CANA_IFRL BUF11 FlexCAN A buffer 11 interrupt 0x0A70 167 CANA_IFRL BUF12 FlexCAN A buffer 12 interrupt...

Page 436: ...upt 0x0C00 192 CANC_IFRL BUF31 BUF16 FlexCAN C buffers 31 16 interrupts 0x0C10 193 CANC_IFRH BUF63 BUF32 FlexCAN C buffers 63 32 interrupts FEC 0x0C20 194 EIR TXF FEC transmit frame flag 0x0C30 195 EI...

Page 437: ...INT40 eDMA channel interrupt 40 0x0DC0 220 EDMA_IRQRH INT41 eDMA channel interrupt 41 0x0DD0 221 EDMA_IRQRH INT42 eDMA channel interrupt 42 0x0DE0 222 EDMA_IRQRH INT43 eDMA channel interrupt 43 0x0DF0...

Page 438: ...B channel 7 interrupt status 0x0FB0 251 ETPU_CISR_B CIS8 eTPU engine B channel 8 interrupt status 0x0FC0 252 ETPU_CISR_B CIS9 eTPU engine B channel 9 interrupt status 0x0FD0 253 ETPU_CISR_B CIS10 eTP...

Page 439: ...A transmit FIFO end of queue flag 0x1150 277 DSPI_ASR TFFF DSPI A Tx FIFO fill flag 0x1160 278 DSPI_ASR TCF DSPI A transmit complete flag 0x1170 279 DSPI_ASR RFDF DSPI A Rx FIFO drain flag FlexCAN B 0...

Page 440: ...11 CAND_IFRL BUF0 FlexCAN D buffer 0 interrupt 0x1380 312 CAND_IFRL BUF1 FlexCAN D buffer 1 interrupt 0x1390 313 CAND_IFRL BUF2 FlexCAN D buffer 2 interrupt 0x13A0 314 CAND_IFRL BUF3 FlexCAN D buffer...

Page 441: ...ral is driven by that flag bit The time from when the peripheral starts to drive its peripheral interrupt request to the INTC to the time that the INTC starts to drive the interrupt request to the pro...

Page 442: ...those comparisons are used to manage the priority of the ISR being executed by the processor The LIFO also assists in managing that priority 10 4 2 1 Current Priority and Preemption The priority arbi...

Page 443: ...IFO stores the preempted PRI values from the INTC_CPR Therefore because these priorities are stacked within the INTC if interrupts need to be enabled during the ISR at the beginning of the interrupt e...

Page 444: ...Interrupt Exception Handler Before the interrupt exception handling completes INTC end of interrupt register INTC_EOIR must be written When it is written the LIFO is popped so that the preempted prior...

Page 445: ...pdated with the preempting peripheral or software settable interrupt request s vector when the interrupt request to the processor is asserted The INTVEC field retains that value until the next time th...

Page 446: ...ests are negated An initialization sequence that allows the peripheral and software settable interrupt requests to generate an interrupt request to the processor is interrupt_request_initialization co...

Page 447: ...he LIFO after the restoration of most of the context and the disabling of processor recognition of interrupts eases the calculation of the maximum stack depth at the cost of postponing the servicing o...

Page 448: ...ure store to clear flag bit has completed lis r3 INTC_EOIR ha form adjusted upper half of INTC_EOIR address li r4 0x0 form 0 to write to INTC_EOIR wrteei 0 disable processor recognition of interrupts...

Page 449: ...h enough to cause preemption the INTC selects the one with the lowest unique vector regardless of the order in time that they asserted However the ability to meet deadlines with this scheduling scheme...

Page 450: ...nates the time when accessing a shared resource that all higher priority interrupts are blocked For example while ISR3 cannot preempt ISR1 while it is accessing the shared resource all of the ISRs wit...

Page 451: ...he number of ISRs In this case group the ISRs with other ISRs that have similar deadlines For example when a priority is allocated for every time the request rate doubles ISRs with request rates aroun...

Page 452: ...d that processor executing the software settable ISR has not completed the work before asking it to again execute that ISR it can check if the corresponding CLRn bit in INTC_SSCIRn is asserted before...

Page 453: ...s of the peripheral or software settable interrupt requests for these other flag bits must be selected properly Their PRIn values in INTC priority select registers INTC_PSR0 INTC_PSR329 must be select...

Page 454: ...INTC_CPR load INTC_IACKR if stacked PRI values are not depleted branch to push_lifo NOTE Reading the INTC_IACKR acknowledges the interrupt request to the processor and updates the INTC_CPR PRI with t...

Page 455: ...Interrupt Controller INTC MPC5566 Microcontroller Reference Manual Rev 2 10 42 Freescale Semiconductor...

Page 456: ...agrams This section contains block diagrams that illustrate the FMPLL the clock architecture and the various FMPLL and clock configurations that are available The following diagrams are provided Figur...

Page 457: ...FM control 1 0 pumps Current controlled oscillator ICO XTAL 0 1 MFD PLLCFG 0 1 MDIS DSPI MCKO_EN MCKO_GT MCKO divider MCKO MDIS EBI MDIS eMIOS MDIS eTPU engines MDIS eSCI MDIS CAN interface CLK FlexCA...

Page 458: ...pumps Current controlled oscillator ICO XTAL MFD PLLCFG 0 1 MDIS DSPI MCKO_EN MCKO_GT MCKO divider MCKO MDIS EBI MDIS eMIOS MDIS eTPU engines MDIS eSCI MDIS CAN interface CLK FlexCAN CLK_SRC Message...

Page 459: ...ivider MCKO MDIS EBI MDIS eMIOS MDIS eTPU engines MDIS eSCI MDIS CAN interface CLK FlexCAN CLK_SRC Message buffer CLK ENGCLK divider CLKOUT divider ENGCLK CLKOUT NPC PLLREF PLLSEL MODE Core INTC eDMA...

Page 460: ...KO divider MCKO MDIS EBI MDIS eMIOS MDIS eTPU engines MDIS eSCI MDIS CAN interface CLK FlexCAN CLK_SRC Message buffer CLK ENGCLK divider CLKOUT divider ENGCLK CLKOUT NPC PLLREF PLLSEL MODE Core INTC e...

Page 461: ...CKO MDIS EBI MDIS eMIOS MDIS eTPU engines MDIS eSCI MDIS CAN interface CLK FlexCAN CLK_SRC Message buffer CLK ENGCLK divider CLKOUT divider ENGCLK CLKOUT NPC PLLREF PLLSEL MODE Core INTC eDMA SIU BAM...

Page 462: ...CFG 0 1 MDIS DSPI MCKO_EN MCKO_GT MCKO divider MCKO MDIS EBI MDIS eMIOS MDIS eTPU engines MDIS eSCI MDIS CAN Interface CLK FlexCAN CLK_SRC Message buffer CLK ENGCLK divider CLKOUT divider ENGCLK CLKOU...

Page 463: ...t the 496 assembly Refer to Section 11 1 4 1 Crystal Reference Default Mode External reference mode Refer to Section 11 1 4 2 External Reference Mode PLL dual controller 1 1 mode for EXTAL_EXTCLK to C...

Page 464: ...or the FMPLL are in Chapter 4 Reset 11 1 4 1 Crystal Reference Default Mode In crystal reference mode the FMPLL receives an input clock frequency Fref_crystal from the crystal oscillator circuit EXTAL...

Page 465: ...L_SYNCR PREDIV 11 1 4 2 External Reference Mode This external reference mode functions the same as crystal reference mode except that EXTAL_EXTCLK is driven by an external clock generator rather than...

Page 466: ...enter bypass mode the default FMPLL configuration must be overridden by following the procedure outlined in Section 11 1 4 FMPLL Modes of Operation A block diagram illustrating bypass mode is shown i...

Page 467: ...all MPC5500s execute an mbar or msync instruction between the write to change the FMPLL_SYNCR MFD and the read to check the lock status shown by FMPLL_SYNSR LOCK Buffered writes to the FMPLL as contr...

Page 468: ...bits In 1 1 dual controller mode the PREDIV bits are ignored and the input clock is fed directly to the analog loop 000 Divide by 1 001 Divide by 2 010 Divide by 3 011 Divide by 4 100 Divide by 5 101...

Page 469: ...o avoid unintentional interrupt requests disable LOLIRQ before changing MFD and then reenable it after acquiring lock 9 Reserved 10 12 RFD 0 2 Reduced frequency divider The RFD bits control a divider...

Page 470: ...en it LOLIRQ is asserted and when LOLF is asserted If either LOLF or LOLIRQ is negated the interrupt request is negated When operating in crystal reference external reference or dual controller mode t...

Page 471: ...9 Expected difference value Holds the expected value of the difference of the reference and the feedback counters Refer to Section 11 4 3 3 FM Calibration Routine to determine the value of these bits...

Page 472: ...an unintentional interrupt clear LOLIRQ before changing MFD or PREDIV or before enabling FM after a previous interrupt and relock occurred 23 LOC Loss of clock status Indicates whether a loss of cloc...

Page 473: ...ins cleared after reset In crystal reference external reference and dual controller mode LOCKS is set after reset 0 PLL has lost lock since last system reset a write to FMPLL_SYNCR to modify the MFD a...

Page 474: ...an be selected as the clock source for the CAN interface in the FlexCAN blocks resulting in very low jitter performance Figure 11 1 shows a block diagram of the FMPLL and the system clock architecture...

Page 475: ...gating are listed in Table 11 6 along with the registers and bits that disable each module The software controlled clocks are enabled when the MCU comes out of reset 11 4 1 3 Clock Dividers Each of th...

Page 476: ...the NPC through the JTAG port Refer to Chapter 25 Nexus Development Interface for more information 11 4 1 3 3 Engineering Clock ENGCLK The engineering clock ENGCLK divider can be programmed to divide...

Page 477: ...ven in Section 11 4 3 2 Programming System Clock Frequency with Frequency Modulation 11 4 2 4 FMPLL Lock Detection A pair of counters monitor the reference and feedback clocks to determine when the sy...

Page 478: ...lock condition occurred To exit reset the reference must be present and the FMPLL must acquire lock In bypass mode the FMPLL cannot lock Therefore a loss of lock condition cannot occur and LOLRE has n...

Page 479: ...reset 11 4 2 6 2 Loss of Clock Reset When a loss of clock condition is recognized reset is asserted if the FMPLL_SYNCR LOCRE bit is set The LOCF and LOC bits in FMPLL_SYNSR are cleared after reset the...

Page 480: ...ts are changed If frequency modulation is going to be enabled the maximum allowable frequency must be reduced by the programmed Fm NOTE Following these steps produces immediate changes in supply curre...

Page 481: ...MPLL_SYNCR Disable LOLIRQ Write FMPLL_SYNCR PREDIV to a desired final value Write FMPLL_SYNCR MFD to a desired final value Write the RFD control field value to a desired final RFD value plus one 3 Wai...

Page 482: ...be programmed for EXP Figure 11 10 illustrates the effects of the parameters and the modulation waveform built into the modulation hardware The modulation waveform is always a triangle wave and its s...

Page 483: ...ccessful attempt again by going back to step 1 7 Initialize the FMPLL to the desired final system frequency by changing FMPLL_SYNCR RFD Note that the FMPLL does not need to re lock when only changing...

Page 484: ...ed value of the difference between the reference and feedback counters used in the calibration of the FM equation For example if 80 MHz is the desired final frequency and an 8 MHz crystal is used the...

Page 485: ...n the COUNT0 register The calibration system then enables modulation at programmed Fm The ICO is given time to settle Both counters are reset and restarted The feedback counter begins to count full IC...

Page 486: ...e 11 11 shows a block diagram of the calibration circuitry and its associated registers Figure 11 12 shows a flow chart showing the steps taken by the calibration circuit Figure 11 11 FM Auto Calibrat...

Page 487: ...nter Allow system 3 x 384 reference counts to settle CAL N 1 Enable FM where N 7 Count M reference clock cycles Store value of feedback Counter in CAL 0 Enter calibration mode Set PCALPASS 1 Let DIFF...

Page 488: ...For an overview of how the EBI used in the MPC5500 differs from the EBI used in MPC500 devices see Section 12 5 5 Summary of Differences from MPC5xx 12 1 1 Block Diagram Figure 12 1 is a block diagra...

Page 489: ...udes single data rate SDR burst mode flash external SRAM and asynchronous memories It supports up to four regions via chip selects each with its own programmed attributes External Bus Interface Memory...

Page 490: ...6 MPC5566 Packaging 416 EBI Address Bus Size 24 bit 1 1 24 bits available In the 416 package three configurations can be used to attain a 24 bit size ADDR 8 11 _GPIO 4 7 can be added to ADDR 12 31 CS...

Page 491: ...Mode In single master mode the EBI responds to internal requests matching one of its regions but ignores all externally initiated bus requests The MCU is the only master allowed to initiate transacti...

Page 492: ...nal system clock This mode is selected by writing the external clock control register in the system integration module SIU_ECCR The configurable bus speed modes supports both or speed modes meaning th...

Page 493: ...12 31 I O Address bus Up 416 496 BDIP Output Burst data in progress Up 416 496 CAL_ADDR 10 11 4 Output Calibration address bus output Up 496 CAL_ADDR 12 30 Output Calibration address bus output Up 49...

Page 494: ...rite transaction to an external device The EBI also drives DATA 0 31 when an external master owns the external bus and initiates a read transaction to an internal module DATA 0 31 is driven by an exte...

Page 495: ...is kept valid until the cycle is terminated See Section 12 4 1 5 Memory Controller with Support for Various Memory Types for details on chip select operation CS 0 3 are implemented in the 496 VertiCal...

Page 496: ...signal TEA is asserted by the EBI when the internal bus monitor detected a timeout error or when an external master initiated a transaction to an internal module and an internal error was detected Th...

Page 497: ...ternal master mode In single master mode the BG signal is never asserted or sampled by the EBI When configured for internal arbitration BG is an output only signal The EBI asserts BG to when an extern...

Page 498: ...ation Chip Selects CAL_CS 0 3 CAL_CS n is asserted by the master to indicate that this transaction is targeted for a particular memory bank on the calibration external bus The calibration chip selects...

Page 499: ...rection EXTM 1 MDIS 0 ADDR 6 11 1 non EBI function Address bus output Address bus I O 2 ADDR 12 30 non EBI function Address bus output Address bus I O 2 BDIP non EBI function Burst data in progress ou...

Page 500: ...t sample them for input 4 This device is designed to support a 32 bit EBI data bus DATA 0 31 and four write byte enable signals WE BE 0 3 using the VertiCal assembly 5 The calibration signals for this...

Page 501: ...eparate from the clock used by the rest of the EBI In module disable mode the clock used by the non register portion of the EBI is disabled to reduce power consumption The dedicated clock signal allow...

Page 502: ...ignored and read as 0 External master mode EXTM 1 allows the external master device to access any internal memory area that is mapped as long as the internal e200z6 core is fully operational Single m...

Page 503: ...BI effectively putting the EBI in a software controlled power saving state See Section 12 1 4 3 Module Disable Mode for more information No external bus accesses can be performed when the EBI is in mo...

Page 504: ...his bit can be cleared by writing a 1 to it 31 BMTF Bus monitor timeout flag Set if the cycle was terminated by a bus monitor timeout 0 No error 1 Bus monitor timeout occurred This bit can be cleared...

Page 505: ...bled for chip select accesses since these always use internal TA and thus have no danger of hanging the system 0 Disable bus monitor 1 Enable bus monitor for non chip select accesses only 25 31 Reserv...

Page 506: ...ip select measured in 32 bit words The number of beats in a burst is automatically determined by the EBI to be 4 8 or 16 according to the port size so that the burst fetches the number of words chosen...

Page 507: ...L_ORn Field Descriptions Field Description 0 16 AM 0 16 Address mask Allows masking of any corresponding bits in the associated base register Masking the address independently allows external devices...

Page 508: ...1 4 Support for External Master Accesses to Internal Addresses The EBI allows an external master to access internal address space when the EBI is configured for external master mode in the EBI_MCR Ext...

Page 509: ...er bank one Figure 12 7 Bank Base Address and Match Structure A match on a valid calibration chip select register overrides a match on any non calibration chip select register with CAL_CS 0 having the...

Page 510: ...any other case besides the special case of 32 bit non chip select writes in 16 bit data bus mode Internal requests to write more than 32 bits such as a cache line externally are broken up into separat...

Page 511: ...nd external bus for calibration See Section 12 4 2 12 Calibration Bus Operation for more details on using the calibration bus 12 4 1 13 Four Write Byte Enable WE BE Signals 416 BGA Package and VertiCa...

Page 512: ...om the other master and needs the other master to stay valid continuously 12 4 1 17 Compatible with MPC5xx External Bus with Some Limitations The EBI is compatible with the external bus of the MPC5xx...

Page 513: ...lfword write to 0 0003 misaligned case 4 with 16 bit port size results in four external 16 bit transfers because of the transfer granularity of 32 bits For Table 12 14 Misalignment Cases Supported by...

Page 514: ...umber 1 1 Misaligned case numbers from Table 12 14 Program Size and Byte Offset Port Size ADDR 30 31 2 3 2 External ADDR pins are not necessarily the address on the internal master AHB bus 3 Addresses...

Page 515: ..._WR TSIZ 0 1 and BDIP The address and its related signals with the exception of TS BDIP are driven on the bus with the assertion of the TS signal and kept valid until the bus master receives TA assert...

Page 516: ...red as single master mode Therefore arbitration is not needed and is not shown in these diagrams See Section 12 4 2 10 Bus Operation in External Master Mode to read how the flow and timing diagrams ch...

Page 517: ...Figure 12 10 Single Beat 32 bit Read Cycle CS Access Zero Wait States Figure 12 11 Single Beat 32 bit Read Cycle CS Access One Wait State DATA is valid CLKOUT ADDR 8 31 TS DATA 0 31 TA RD_WR TSIZ 0 1...

Page 518: ...gure 12 12 Single Beat 32 bit Read Cycle Non CS Access Zero Wait States 00 DATA is valid The EBI drives address and control signals an extra cycle because it version of the external TA 1 cycle delayed...

Page 519: ...e beat write cycle are illustrated in the following flow and timing diagrams Figure 12 13 Basic Flow Diagram of a Single Beat Write Cycle Yes No Receives address Asserts transfer start TS drives addre...

Page 520: ...e 12 14 Single Beat 32 bit Write Cycle CS Access Zero Wait States Figure 12 15 Single Beat 32 bit Write Cycle CS Access One Wait State 00 DATA is valid CLKOUT ADDR 8 31 TS DATA 0 31 TA RD_WR TSIZ 0 1...

Page 521: ...Figure 12 20 and Figure 12 21 Besides this dead cycle in most cases back to back accesses on the external bus do not cause any change in the timing from that shown in the previous diagrams and the tw...

Page 522: ...gure 12 17 Back to Back 32 bit Reads to the Same CS Bank Figure 12 18 Back to Back 32 bit Reads to Different CS Banks 00 DATA is valid DATA is valid CLKOUT ADDR 8 31 TS DATA 0 31 TA RD_WR TSIZ 0 1 BDI...

Page 523: ...EBI MPC5566 Microcontroller Reference Manual Rev 2 12 36 Freescale Semiconductor Figure 12 19 Write After Read to the Same CS Bank ADDR 8 31 TS DATA 0 31 TA RD_WR DATA is valid TSIZ 0 1 BDIP WE CS n D...

Page 524: ...PC5566 Microcontroller Reference Manual Rev 2 Freescale Semiconductor 12 37 Figure 12 20 Back to Back 32 bit Writes to the Same CS Bank CLKOUT ADDR 8 31 TS DATA 0 31 TA RD_WR TSIZ 0 1 BDIP WE CS n 00...

Page 525: ...es to external devices that use the chip selects1 Accesses from an external master or to devices operating without a chip select are always single beat If an internal request to the EBI indicates a si...

Page 526: ...ed atomic by the EBI so the EBI does not allow other unrelated master accesses or bus arbitration to intervene between the transfers For more details and a timing diagram see Section 12 4 2 6 3 Small...

Page 527: ...2 22 Basic Flow Diagram of a Burst Read Cycle No Yes Receives address Asserts transfer start TS Drives address and attributes Master Next to last data beat Slave Drives data Asserts transfer acknowled...

Page 528: ...bit Read Cycle Zero Wait States Figure 12 24 Burst 32 bit Read Cycle One Initial Wait State CLKOUT ADDR 8 31 BDIP DATA 0 31 TA RD_WR TSIZ 0 1 TS OE CS n Expects more data ADDR 29 31 000 00 DATA is va...

Page 529: ...base register results in BDIP being asserted SCY 1 cycles after the address transfer phase and being held asserted throughout the cycle regardless of the wait states between beats BSCY Figure 12 25 sh...

Page 530: ...n PS are set such that one of two situations occur Burst accesses are inhibited and the number of bytes requested by the master is greater than the port size 16 or 32 bit can accommodate in a single a...

Page 531: ...all Access Example 2 32 byte Write with External TA The following sections show a few examples of small accesses The timing for the remaining cases in Table 12 17 can be extrapolated from these and th...

Page 532: ...Write with External TA Figure 12 28 shows an example of a 32 byte write to a non chip select device such as an external master using external TA requiring eight 32 bit external transactions Due to th...

Page 533: ...d then masking out the lower 4 bits to fix them at zero Table 12 18 Examples of 4 word Burst Addresses First Address Lower 5 bits of the First Address 0x10 no carry Final Second Address after masking...

Page 534: ...l masters are supported the EBI naturally aligns the accesses when it sends them out to the external bus splitting them into multiple aligned accesses if necessary Natural alignment for the EBI means...

Page 535: ...requires that the portion of the data bus used for a transfer to from a particular port size be fixed A 32 bit port must reside on data bus bits 0 31 and a 16 bit port must reside on bits 0 15 The fi...

Page 536: ...er Size TSIZ 0 1 Address 32 Bit Port Size 16 Bit Port Size 1 1 Also applies when DBM 1 for 16 bit data bus mode A 30 A 31 D 0 7 D 8 15 D 16 23 D 24 31 D 0 7 D 8 15 Byte 01 0 0 OP0 OP0 01 0 1 OP1 OP1 0...

Page 537: ...nsure that no other master is driving the bus before it can assert bus busy to assume ownership of the bus The new master must sample bus busy negated for two cycles before asserting bus busy to avoid...

Page 538: ...to back accesses without rearbitration as long as it is still receiving BG asserted If BG is negated during a transaction the MCU must rearbitrate for the bus before the next transaction The determina...

Page 539: ...ter and the current master start another access without re arbitrating for the bus If the priority field is configured for unequal priority between internal and external masters then whenever requests...

Page 540: ...master is configured for external arbitration master 1 In this case the BR signals of each master are connected together since only master 1 drives BR The BG signals of each master are also connected...

Page 541: ...le for Internal Arbiter State Outputs Previous Inputs External Status Next State BG BB 1 BR 2 BB 3 MCU internal request pending IRP 4 External has higher priority EHP 5 MCU external transaction in pro...

Page 542: ...xternal master BG 0 previous BB 1 during the previous 3 cycles 8 RGB is always low in this state thus it is ignored in the transition logic 9 RGB is always low in this state thus it is ignored in the...

Page 543: ...n required as seen in Figure 12 37 However the DATA does not need to be held one cycle longer by the slave because the EBI latches DATA every cycle during non chip select accesses During these accesse...

Page 544: ...master asserts TEA to timeout a transaction to an internal address on the MCU the EBI cannot terminate the transfer internally Therefore subsequent TS assertions by the external master are not servic...

Page 545: ...sed for the externally driven TEA and TA TA 1 Action Negated Negated No termination Asserted Transfer error termination Negated Asserted Normal transfer termination The EBI drives address and control...

Page 546: ...accesses it takes ownership on the external bus and the direction of most of the bus signals is inverted relative to its direction when the MCU owns the bus To operate two masters in external master m...

Page 547: ...mode The external address is compared for any external master access to determine if EBI operation is required Because only 24 address bits are available on the external bus decoding logic is require...

Page 548: ...or TEA If the access was successfully completed the MCU asserts TA and the external master can proceed with another external master access or relinquish the bus If an address or data error was detecte...

Page 549: ...cycles Negates BR if no other requests No Yes External master has priority Negates BG if asserted Asserts bus busy BB if no other master is driving Assert transfer start TS drives address and attribut...

Page 550: ...ernal Master has Priority Negates BG if Asserted Asserts Bus Busy BB if No Other Master is Driving Assert Transfer Start TS Drives Address and Attributes Receives Address No Yes Address in Internal Me...

Page 551: ...ernal module is being accessed and how much internal bus traffic is going on at the time of the access Figure 12 41 External Master Read from MCU Receive bus grant and bus busy negated for second cycl...

Page 552: ...BI then DATA remains valid as shown due to use of latched TA internally These extra data valid cycles past TA are not required by the slave EBI as shown due to use of latched TA internally This extra...

Page 553: ...ng operations writes bursts etc add the arbitration sequence to the flow and timing diagrams shown for single master mode See Section 12 4 2 4 Single Beat Transfer and Section 12 4 2 5 Burst Transfer...

Page 554: ...e external master is configured for external arbitration Figure 12 45 shows an external master read followed by an MCU read to the same chip select bank Figure 12 46 shows an MCU read followed by an e...

Page 555: ...followed by MCU Read to Same CS Bank DATA is valid DATA is valid External master and MCU off External master starts read access Receive bus grant and bus busy negated for second cycle Using the intern...

Page 556: ...owed by External Master Read to Different CS Bank MCU starts read access Receive bus busy negated for second cycle External master and MCU off Using the internal arbiter External master starts read ac...

Page 557: ...EBI master and EBI slave as the external master is expected to be another MCU with this EBI For this case a special two beat burst protocol is used for reads and writes so that the EBI slave can inte...

Page 558: ...al master in 16 bit data bus mode Figure 12 48 External Master 32 bit Read from MCU with DBM 1 Receive bus grant and bus busy negated for second cycle Assert BB drive address and assert TS Using the i...

Page 559: ...to back accesses can switch from one bus to the other as determined by the type of chip select each address matches The timing diagrams and protocol for the calibration bus are identical to those for...

Page 560: ...out the boot modes supported by the MCU booting is not possible from external memory on the calibration bus If code in external memory must write EBI registers avoid modifying EBI registers while exte...

Page 561: ...the asynchronous memory just as done for a synchronous memory 12 5 3 1 Example Wait State Calculation This example applies to any chip select memory synchronous or asynchronous As an example say we h...

Page 562: ...to Asynchronous Memory Figure 12 53 shows a timing diagram of a read operation to a 16 bit asynchronous memory using three wait states Figure 12 53 Read Operation to Asynchronous Memory Three Initial...

Page 563: ...le Semiconductor Figure 12 54 shows a timing diagram of a write operation to a 16 bit asynchronous memory using three wait states Figure 12 54 Write Operation to Asynchronous Memory Three Initial Wait...

Page 564: ...use external TA instead must use wait state configuration No memory controller support for external masters must configure each master in multi master system to drive its own chip selects Changes in...

Page 565: ...ory management unit MMU in e200z6 core Removed support for 8 bit ports Removed boot chip select operation on chip boot assist module BAM handles boot and configuration of EBI registers Open drain mode...

Page 566: ...wing for field reprogramming without requiring external programming voltage sources The module is a solid state silicon memory device consisting of blocks of single transistor storage elements The dev...

Page 567: ...ayed non volatile storage elements sense amplifiers row selects column selects charge pumps ECC logic and redundancy logic The arrayed storage elements in the flash core are subdivided into physically...

Page 568: ...ion of other memory types The flash memory array has the following features Software programmable block program erase restriction control for low mid and high address spaces Erase of selected blocks E...

Page 569: ...al flash has a feature that allows the internal flash timing to be modified to emulate an external memory hence the name external emulation mode The upper five address lines are used to provide additi...

Page 570: ...0x0A2F_FFFF 10010 18 0x0B00_0000 0x0B2F_FFFF 11010 26 0x0C00_0000 0x0C2F_FFFF 00011 3 0x0D00_0000 0x0D2F_FFFF 01011 11 0x0E00_0000 0x0E2F_FFFF 10011 19 0x0F00_0000 0x0F2F_FFFF 11011 27 0x1000_0000 0x1...

Page 571: ...ase address 0x00FF_FC00 Array base address 0x0000_0000 Control registers base address 0xC3F8_8000 Table 13 3 Module Flash Array Memory Map Byte Address Type and Amount of Space Used Access Shadow base...

Page 572: ...ay base 0x0006_0000 M1 128 KB Array base 0x0008_0000 High address space H0 128 KB 4 Array base 0x000A_0000 H1 128 KB Array base 0x000C_0000 H2 128 KB 5 Array base 0x000E_0000 H3 128 KB Array base 0x00...

Page 573: ...t support RWW Refer to Section 13 4 2 5 Flash Shadow Block Table 13 5 Module Register Memory Map Byte Address Register Name Register Description Bits Register base 0x0000 FLASH_MCR Module configuratio...

Page 574: ...0 0 SIZE 0 LAS 0 0 0 MAS W Reset 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R EER RWE 1 1 PEAS DONE PEG 0 0 STOP 0 PGM PSUS ERS ESUS EHV W w1c w1c Reset 0 0 1 1 0...

Page 575: ...program erase and main address space disabled 21 DONE State machine status Indicates if the flash module is performing a high voltage operation DONE is set to a 1 on termination of the flash module r...

Page 576: ...ogram suspend and clear DONE while EHV is low PSUS is cleared on reset 0 Program sequence is not suspended 1 Program sequence is suspended 29 ERS Erase Used to set up flash for an erase operation A 0...

Page 577: ...with DONE high PSUS and ESUS low terminates the current program erase high voltage operation When an operation is aborted2 there is a 1 to 0 transition of EHV with DONE low and the suspend bit for th...

Page 578: ...rom being modified These bits along with bits in the secondary LMLOCK field FLASH_SLMLR determine if the block is locked from program or erase An OR of FLASH_LMLR and FLASH_SLMLR determine the final l...

Page 579: ...itable unless LME is high 0 Shadow row is available to receive program and erase pulses 1 Shadow row is locked for program and erase 12 13 Reserved 14 15 MLOCK 1 0 Mid address block lock A value of 1...

Page 580: ...sh values in the shadow row An erased array causes the reset value to be 1 Figure 13 7 High Address Space Block Locking Register FLASH_HLR Table 13 9 FLASH_HLR Field Descriptions Field Description 0 H...

Page 581: ...ow and mid address locks are disabled and cannot be modified 1 Secondary low and mid address locks are enabled to be written 1 10 Reserved 11 SSLOCK Secondary shadow lock An alternative method to use...

Page 582: ...rite is completed or if a high voltage operation is suspended In the event that blocks are not present due to configuration or total memory size the corresponding SELECT bits default to unselected and...

Page 583: ...eserved 12 31 HBSEL 19 0 High address space block select Has the same characteristics as MSEL For more information refer to Section 13 3 2 5 Low Mid Address Space Block Select Register FLASH_LMSR 0b00...

Page 584: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 13 11 Address Register FLASH_AR Table 13 13 FLASH_AR Field Descriptions Field Description 0 9 Reserved 10 28 ADDR 3 21 Doubleword a...

Page 585: ...g for array writes This field must be set to a value corresponding to the operating frequency of the system clock The required settings are documented in Table 13 15 00 Reserved 01 One wait state 10 T...

Page 586: ...uffer hit or miss 111 Reserved 31 BFEN FBIU line read buffers enable Enables or disables line read buffer hits It is also used to invalidate the buffers These bits are cleared by hardware reset 0 The...

Page 587: ...uffer fills Prefetch triggering can be restricted to instruction accesses only data accesses only or can be unrestricted Prefetch triggering can also be controlled on a per master basis Address Base 0...

Page 588: ...of a protection violation results in an error response from the Flash BIU to the system bus 13 4 1 3 Flash Read Cycles Buffer Miss Read data is normally stored in the least recently updated line read...

Page 589: ...alid data which has been prefetched to satisfy a potential future access Busy the buffer is currently being used to satisfy a burst read Busy fill the buffer has been allocated to receive data from th...

Page 590: ...or primary wait states When these inputs are non zero additional cycles are added to system bus transfers Normal system bus termination is extended In addition no line read buffer prefetches are initi...

Page 591: ...tion 13 3 2 4 Secondary Low Mid Address Space Block Locking Register FLASH_SLMLR for more information 13 4 2 2 Read While Write RWW The flash core is divided into partitions Partitions are always comp...

Page 592: ...mmed write each additional address in the page with data to be programmed This is referred to as a program data write All unwritten data words default to 0xFFFF FFFF 4 Write a logic 1 to the FLASH_MCR...

Page 593: ...odule to step 8 of the program sequence An aborted program results in FLASH_MCR PEG being set low indicating a failed operation The data space being operated on before the abort contains indeterminate...

Page 594: ...User mode read state PEG 0 Read MCR DONE 1 DONE 0 Write MCR PSUS 0 EHV 1 Abort WRITE EHV 0 Step 5 Step 6 PEG Success PEG 1 Write MCR Failure PEG 0 Step 7 EHV 0 PGM More words Step 8 No Yes Write MCR...

Page 595: ...ded until FLASH_MCR DONE 1 At this time flash core reads can be attempted After it is suspended the flash core can only be read Reads to the blocks being programmed erased return indeterminate data Th...

Page 596: ...interlock writes are ignored The user can terminate the erase sequence by clearing FLASH_MCR ERS before setting FLASH_MCR EHV An erase operation can be aborted by clearing FLASH_MCR EHV assuming FLAS...

Page 597: ...e read or a program sequence can be initiated erase suspended program Before initiating a program sequence the user must first clear FLASH_MCR EHV If a program sequence is initiated the value of the F...

Page 598: ...suspend ERS 0 User mode read state PEG 0 Read MCR DONE 1 DONE 0 Write MCR ESUS 0 EHV 1 Abort WRITE EHV 0 Step 5 Step 6 PEG Success PEG 1 Write MCR Failure PEG 0 Step 7 EHV 0 Erase more blocks Step 8...

Page 599: ...for user defined functions or other configuration words The shadow block can be locked unlocked against program or erase by using the FLASH_LMLR or FLASH_SLMLR discussed in Section 13 3 2 Register Des...

Page 600: ...ess is disabled Flash access is any read write or execute access Table 13 17 Flash Access Disable Logic BOOTCFG1 0 1 1 BOOTCFG 0 1 bits are located in the SIU_RSR Censorship Control 0x00FF_FDE0 Upper...

Page 601: ...value to internal flash 13 4 3 Flash Memory Array Stop Mode Stop mode is entered by setting the FLASH_MCR STOP bit The FLASH_MCR STOP bit cannot be written when FLASH_MCR PGM 1 or FLASH_MCR ERS 1 In s...

Page 602: ...ze register and status bits to their default reset values If the flash is executing a program or erase operation and a reset is issued the operation is aborted and the flash disables the high voltage...

Page 603: ...Flash Memory MPC5566 Microcontroller Reference Manual Rev 2 13 38 Freescale Semiconductor...

Page 604: ...ource for standby operation Byte halfword word and doubleword addressable Single bit correction and double bit error detection 14 2 SRAM Operating Modes Table 14 1 lists and describes the SRAM operati...

Page 605: ...rects all 1 bit errors Detects and flags all 2 bit errors as non correctable errors Detects 72 bit reads 64 bit data bus plus the 8 bit ECC that return all zeros or all ones asserts an error indicator...

Page 606: ...operation Lists the type of SRAM operation executing currently Previous operation Lists the valid types of SRAM operations that can precede the current SRAM operation valid operation during the preced...

Page 607: ...rite to each SRAM location in the application initialization code to initialize the SRAM array All writes must specify an even number of registers performed on 64 bit word aligned boundaries If the wr...

Page 608: ...single 64 bit write The following example code illustrates the use of the stmw instruction to initialize the SRAM ECC bits init_RAM lis r11 0x4000 base address of the SRAM 64 bit word aligned ori r11...

Page 609: ...SRAM MPC5566 Microcontroller Reference Manual Rev 2 14 6 Freescale Semiconductor...

Page 610: ...sceiver connection information for both the 10 and 100 Mbps MII media independent interface as well as the 7 wire serial interface Additionally detailed descriptions of operation and the programming m...

Page 611: ...rface CSR FIFO DMA Descriptor controller MII Receive Transmit Bus controller controller FEC_MDC FEC_MDIO FEC_RX_CLK FEC_RX_DV FEC_RXD 3 0 FEC_RX_ER FEC_TX_CLK FEC_TX_EN FEC_TXD 3 0 FEC_TX_ER FEC_CRS M...

Page 612: ...thernet controller and is divided into transmit and receive FIFOs The FIFO boundaries are programmable using the FRSR register Application data flows to from the DMA block from to the receive transmit...

Page 613: ...s utilization Automatic internal flushing of the receive FIFO for runts collision fragments and address recognition rejects no system bus utilization Address recognition Frames with a broadcast addres...

Page 614: ...for a description of how to read and write registers in the transceiver using this interface 15 2 2 2 10 Mpbs 7 Wire Interface Operation The FEC supports a 7 wire interface as used by many 10 Mbps Et...

Page 615: ...se the FEC is a system bus master errant writes can corrupt any part of the system memory map Errant writes to documented FEC memory locations can also result is data corruption 15 3 3 MIB Block Count...

Page 616: ...byte packets 0x022C RMON_T_P65TO127 RMON TX 65 to 127 byte packets 0x0230 RMON_T_P128TO255 RMON TX 128 to 255 byte packets 0x0234 RMON_T_P256TO511 RMON TX 256 to 511 byte packets 0x0238 RMON_T_P512TO1...

Page 617: ...N_R_P128TO255 RMON RX 128 to 255 byte packets 0x02B4 RMON_R_P256TO511 RMON RX 256 to 511 byte packets 0x02B8 RMON_R_P512TO1023 RMON RX 512 to 1023 byte packets 0x02BC RMON_R_P1024TO2047 RMON RX 1024 t...

Page 618: ...ccess User R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R FXS BE0 FXS BE1 0 FXS BE3 0 0 FXS BE6 FXS BE7 RBEN WBEN ACC ERR 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 2...

Page 619: ...f the burst completed without error before it actually writes the data so that it can fetch the second half of the write data from the FIFO When actually written onto the system bus the first half of...

Page 620: ...ver are HBERR BABR BABT LC and RL Interrupts resulting from internal errors are HBERR and UN Some of the error interrupts are independently counted in the MIB block counters Software can mask the foll...

Page 621: ...as initiated by the reception of a valid full duplex flow control pause frame is now complete See Section 15 4 10 Full Duplex Flow Control 4 TXF Transmit frame interrupt This bit indicates that a fram...

Page 622: ...tor ring polling until the bit is set again signifying that additional descriptors were placed into the receive descriptor ring The RDAR register is cleared at reset and when ECR ETHER_EN is cleared A...

Page 623: ...the transmit descriptor ring The TDAR register is cleared at reset when ECR ETHER_EN is cleared or when ECR RESET is set Address Base 0x0010 Access User R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0...

Page 624: ...0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 15 7 Ethernet Control Register ECR Table 15 8 ECR Field Descriptions Bits Description 0 29 Reserved 30 ETHER_EN When this bit is set the FEC is enabled and reception a...

Page 625: ...ith the IEEE 802 3 MII definition To generate an IEEE 802 3 compliant MII management interface write frame write to a PHY register the application must write 01 01 PHYAD REGAD 10 DATA to the MMFR regi...

Page 626: ...written except for the DATA field contents that are replaced by the value read from the PHY register If the MMFR register is written while frame generation is in progress the frame contents is altered...

Page 627: ...2 8 MIB Control Register MIBC The MIBC is a read write register used to provide control of and to observe the state of the MIB block This register is accessed by the application if there is a need to...

Page 628: ...0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 15 10 MIB Control Register MIBC Table 15 12 MIBC Field Descripti...

Page 629: ...me reject If asserted frames with DA destination address FF_FF_FF_FF_FF_FF is rejected unless the PROM bit is set If both BC_REJ and PROM 1 then frames with broadcast DA is accepted and the M MISS bit...

Page 630: ...me the GRA interrupt in the EIR register is asserted With transmission of data frames stopped the MAC transmits a MAC Control PAUSE frame Next the MAC clears the TFC_PAUSE bit and resumes transmitting...

Page 631: ...AUSE frames This register is not reset and must be initialized by the application Table 15 15 describes the field and function in the physical address low register PALR Address Base 0x00E4 Access User...

Page 632: ...Duration Register OPD The OPD is read write accessible This register contains the 16 bit OPCODE and 16 bit pause duration PAUSE_DUR fields used in transmission of a PAUSE frame The OPCODE field is a c...

Page 633: ...ble match with the DA field of receive frames with an individual DA This register is not reset and must be initialized by the application Address Base 0x00EC Access User R W 0 1 2 3 4 5 6 7 8 9 10 11...

Page 634: ...4 25 26 27 28 29 30 31 R IADDR1 W Reset U U U U U U U U U U U U U U U U 1 U signifies a bit that is uninitialized See the Preface of the book Figure 15 18 Descriptor Individual Upper Address Register...

Page 635: ...ld Descriptions Field Description 0 31 IADDR2 The lower 32 bits of the 64 bit hash table used in the address recognition process for receive frames with a unicast address Bit 31 of IADDR2 contains has...

Page 636: ...W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R GADDR2 W Reset U1 U U U U U U U U U U U U U U U 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R GADDR2 W Reset U U U U U U U U U U U U U U U U 1 U signifie...

Page 637: ...the address programmed into the FRSR The receive FIFO uses addresses from FRSR to FRBR inclusive The FRSR register is initialized by hardware at reset FRSR only needs to be written to change the defa...

Page 638: ...0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 R_FSTART 0 0 W Reset 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 Figure 15 24 FIFO Receive Start R...

Page 639: ...ceive buffers Note that because receive frames are truncated at 2K 1 byte only bits 21 27 are used This value must take into consideration that the receive CRC is always written into the last receive...

Page 640: ...registers are reset due to hardware reset which are reset by the FEC RISC and what locations the application must initialize prior to enabling the FEC 15 4 1 1 Hardware Controlled Initialization In th...

Page 641: ...initialization are defined in Table 15 29 FEC FIFO DMA registers that require initialization are defined in Table 15 30 Table 15 28 ECR ETHER_EN De Assertion Effect on FEC Register Machine Reset Value...

Page 642: ...an MII interface for 10 100 Mbps Ethernet and a 7 wire serial interface for 10 Mbps Ethernet The interface mode is selected by the RCR MII_MODE bit In MII mode RCR MII_MODE 1 there are 18 signals def...

Page 643: ...O However the controller defers the transmission if the network is busy FEC_CRS asserts Before transmitting the controller waits for carrier sense to become inactive then determines if carrier sense s...

Page 644: ...CR register When the TCR GTS is set the FEC transmitter stops immediately if transmission is not in progress otherwise it continues transmission until the current frame either finishes or terminates w...

Page 645: ...Ethernet controller receives serial data LSB first 15 4 8 Ethernet Address Recognition The FEC filters the received frames based on the type of destination address DA individual unicast group multicas...

Page 646: ...arly if the DA is a broadcast address broadcast reject RCR BC_REJ is asserted and promiscuous mode is enabled then the frame is accepted and the MISS bit in the receive buffer descriptor is set otherw...

Page 647: ...er If the CRC generator selects a bit that is set in the hash table the frame is accepted otherwise it is rejected For example if eight group addresses are stored in the hash table and random group ad...

Page 648: ...ff ff ff ff 0x2 2 35 ff ff ff ff ff 0x3 3 B5 ff ff ff ff ff 0x4 4 95 ff ff ff ff ff 0x5 5 D5 ff ff ff ff ff 0x6 6 F5 ff ff ff ff ff 0x7 7 DB ff ff ff ff ff 0x8 8 FB ff ff ff ff ff 0x9 9 BB ff ff ff ff...

Page 649: ...ff ff ff ff ff 0x27 39 7F ff ff ff ff ff 0x28 40 4F ff ff ff ff ff 0x29 41 1F ff ff ff ff ff 0x2A 42 3F ff ff ff ff ff 0x2B 43 BF ff ff ff ff ff 0x2C 44 9F ff ff ff ff ff 0x2D 45 DF ff ff ff ff ff 0x...

Page 650: ...ransmit backoff timer hardware which is used for tracking the appropriate collision backoff time in half duplex mode The pause timer increments once every slot time until OPD PAUSE_DUR slot times have...

Page 651: ...2 ones If the collision occurs during the preamble sequence the JAM pattern is sent after the end of the preamble sequence If a collision occurs within 512 bit times the retry process is initiated The...

Page 652: ...is asserted if enabled in the EIMR register 15 4 14 1 3 Late Collision When a collision occurs after the slot time 512 bits starting at the preamble the FEC terminates transmission All remaining buffe...

Page 653: ...receive frame length exceeds MAX_FL bytes the BABR interrupt is generated and the LG bit in the end of frame RxBD is set The frame is not truncated unless the frame length exceeds 2047 bytes 15 4 14...

Page 654: ...urce address length type fields so this must be provided by the driver in one of the transmit buffers The Ethernet MAC can append the Ethernet CRC to the frame Whether the CRC is appended by the MAC o...

Page 655: ...the driver can assign a default receive buffer length large enough to contain an entire frame keeping in mind that a malfunction on the network or an implementation that is not within the specificatio...

Page 656: ...tten by the FEC 0 The buffer is not the last in a frame 1 The buffer is the last in a frame Offset 0 Bits 5 6 Reserved Offset 0 Bit 7 M Miss Written by the FEC This bit is set by the FEC for frames th...

Page 657: ...an integral number of octets in length This bit is valid only if the L bit is set Offset 0 Bit 14 OV Overrun Written by the FEC A receive FIFO overrun occurred during frame reception If this bit is se...

Page 658: ...application once this bit is set Offset 0 Bit 1 TO1 Transmit software ownership This field is reserved for software use This read write bit is not modified by hardware nor does its value affect hardwa...

Page 659: ...written by the application Data length is the number of octets the FEC must transmit from this BD s data buffer It is never modified by the FEC Bits 0 10 are used by the DMA engine bits 11 15 are igno...

Page 660: ...MCU memory space The BAM program supports several booting modes Internal flash External memory without bus arbitration External memory with bus arbitration Serial boot using an eSCI interface Serial...

Page 661: ...e VLE code Configurable external data bus for 16 or 32 bit wide 416 and 496 PBGA packages only 16 1 3 Modes of Operation 16 1 3 1 Normal Mode In normal operation the BAM responds to all read requests...

Page 662: ...rPC Book E or Power Architecture instruction set mode 16 2 Memory Map The BAM has 16 KB of memory from 0xFFFF_C000 through 0xFFFF_FFFF which is divided into four 4 KB segments each containing a copy o...

Page 663: ...apped to physical addresses in internal flash memory This allows code developed to run from external memory to run from internal flash memory The BAM program reads the following data and determines th...

Page 664: ..._55AA which uses a password in internal flash to activate serial boot mode for an uncensored public device Table 16 3 Boot Modes BOOTCFG 0 1 Censorship Control 0x00FF_FDE0 Serial Boot Control 0x00FF_F...

Page 665: ...Serial boot flash password starts at address 0x00FF_FDD8 Address 0x00FF_FDE0 Value 0x55AA MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Binary value 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 Hex value 5 5 A A Censo...

Page 666: ...uration Halfword A valid RCHW is a 16 bit value that contains a constant 8 bit boot identifier and configuration bits refer to Section 4 4 3 5 1 Reset Configuration Halfword Definition The RCHW is the...

Page 667: ...by CS 0 16 3 2 2 1 External Boot MMU Configuration As shown in Table 16 5 the BAM program sets up two MMU regions differently than in internal flash boot mode refer to Table 16 2 The internal flash lo...

Page 668: ...ation mode and configure all other masters to boot using external boot with external arbitration mode The EBI configuration differs for these modes The boot modes are specified by the BOOTCFG 0 1 valu...

Page 669: ...PCR Value Function PCR Value ADDR 8 31 GPIO GPIO ADDR 8 31 0x0440 ADDR 8 31 0x0440 DATA 16 31 GPIO GPIO GPIO or DATA 16 31 4 4 If the BAM reads a valid RCHW with the PS0 bit clear DATA 16 31 are recon...

Page 670: ...esignated as scratch pad SRAM Flash memory map unit MMU TLB entries Watchdog timer is enabled and set to 2 5 227 system clock cycles Serial boot mode downloads 64 bit password 32 bit start address 32...

Page 671: ...configured to operate at a baud bit rate equal to the system clock frequency divided by 60 with one message buffer MB using the standard 11 bit identifier format detailed in the CAN 2 0A specificatio...

Page 672: ...ud rates The BAM ignores the following eSCI errors Overrun errors Noise errors Framing errors Parity errors All data received is assumed to be good and is echoed out on the TXD signal It is the respon...

Page 673: ...nload the 64 bit password 2 Download the start address VLE flag and the number of data bytes to download 3 Download the data 4 Execute the boot code from the start address 12 18 14400 300 K 18 6 16 24...

Page 674: ...tep in the protocol can be performed 2 Download the start address VLE bit and the download size The host computer must send a FlexCAN message with an ID 0x012 that contains 32 bit start address in int...

Page 675: ...ress of the downloaded code as specified in step 2 NOTE The code that downloads and executes must Periodically refresh the e200z6 watchdog timer or Change the timeout period to a value that does not c...

Page 676: ...n the shadow row of internal flash memory If Nexus is enabled the MCU is not censored or is booting from external flash and the password is compared to the constant value of 0xFEED_FACE_CAFE_BEEF If t...

Page 677: ...general purpose inputs The BAM branches to the starting address where the downloaded code is stored specified in step 2 and executes the code NOTE The code that downloads and executes must periodicall...

Page 678: ...Boot Assist Module BAM MPC5566 Microcontroller Reference Manual Rev 2 Freescale Semiconductor 16 19 16 3 3 Interrupts No interrupts are generated or enabled by the BAM...

Page 679: ...Boot Assist Module BAM MPC5566 Microcontroller Reference Manual Rev 2 16 20 Freescale Semiconductor...

Page 680: ...Manual Rev 2 Freescale Semiconductor 17 1 Chapter 17 Enhanced Modular Input Output Subsystem eMIOS 17 1 Introduction This chapter describes the enhanced modular input output subsystem eMIOS which can...

Page 681: ...k Enhanced Modular Unified STAC client submodule BIU Slave interface Clock prescaler Output disable control bus Note 1 Connection between UC n 1 and UCn necessary to implement QDEC mode Input Output S...

Page 682: ...counter Internal prescaler Dedicated output pin for buffer direction control Selectable time base Can generate its own time base Four 24 bit wide counter buses Counter bus A can be driven by unified...

Page 683: ...modulation buffered These modes are described in Section 17 4 4 4 Unified Channel Operating Modes Table 17 1 eMIOS Operating Modes Mode Description User User mode is the normal operating mode When EM...

Page 684: ...IOS Output Disable Input Signals 17 2 1 External Signals When configured as an input EMIOSn is synchronized and filtered by the programmable input filter PIF The output of the PIF is then used by the...

Page 685: ...hannel has selected output disable capability by the setting of its EMIOS_CCRn ODIS bit and by specifying the output disable input in its EMIOS_CCRn ODISSL field eTPU Output Disable Input Signal3 3 ET...

Page 686: ...isters 256 Base 0x0200 UC15 Unified channel 15 registers 256 Base 0x0220 UC16 Unified channel 16 registers 256 Base 0x0240 UC17 Unified channel 17 registers 256 Base 0x0260 UC18 Unified channel 18 reg...

Page 687: ...sed to stop the clock of the module except the access to registers EMIOS_MCR and EMIOS_OUDR 0 Clock is running 1 Enter low power mode 2 FRZ Freeze Enables the eMIOS to freeze the registers in the unif...

Page 688: ...C Client Submodule and the shared time and angle clock STAC bus interface section and the STAC bus configuration register ETPU_REDCR section of the eTPU chapter for more information about the STAC 5 G...

Page 689: ...F2 F1 F0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 17 3 eMIOS Global Flag Register EMIOS_GFR Address Base 0x0008 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 OU23 OU22 OU21...

Page 690: ...ed by reset Table 17 8 summarizes the EMIOS_CBDRn writing and reading accesses for all operating modes Refer to Section 17 4 4 4 Unified Channel Operating Modes for more information NOTE The EMIOS_CBD...

Page 691: ...ter Access Write Read Write Read Alternate Read GPIO A1 A2 A1 B1 B2 B1 SAIC1 A2 B2 B2 SAOC1 1 In these modes the register EMIOS_CBDRn is not used but B2 can be accessed A2 A1 B2 B2 IPWM A2 B1 IPM A2 B...

Page 692: ...ong these controls are the setting of a channel prescaler channel mode selection input trigger sensitivity and filtering interrupt and DMA request enabling and output mode control Address UCn Base 0x0...

Page 693: ...signal is asserted the output pin goes to the complement of EDPOL for OPWFM OPWFMB and OPWMB modes but the unified channel continues to operate normally that is it continues to produce FLAG and matche...

Page 694: ...DMA 8 Reserved Table 17 9 EMIOS_CCRn Field Description continued Field Description eMIOS Channel DMA 0 DMA 1 0 Interrupt DMA request 1 Interrupt DMA request 2 Interrupt DMA request 3 Interrupt DMA req...

Page 695: ...leared by reset and is always read as zero This bit is valid for every output operating mode which uses comparator A otherwise it has no effect 0 Has no effect 1 Force a match at comparator A For inpu...

Page 696: ...L bit When not shown in the mode of operation description this bit has no effect 0 Single edge triggering defined by the EDPOL bit 1 Both edges triggering For GPIO input mode the EDSEL bit selects if...

Page 697: ...e count direction according to the phase difference 0 Internal counter decrements if phase_A is ahead phase_B signal 1 Internal counter increments if phase_A is ahead phase_B signal NOTE To operate pr...

Page 698: ...pulse width and frequency modulation FLAG set at match of internal counter and comparator B immediate update 0011001 Output pulse width and frequency modulation FLAG set at match of internal counter...

Page 699: ...cy modulation buffered FLAG set at match of internal counter and comparator B 1011001 Reserved 1011010 Output pulse width and frequency modulation buffered FLAG set at match of internal counter and co...

Page 700: ...l Status Register EMIOS_CSRn Table 17 11 EMIOS_CSRn Field Descriptions Field Description 0 OVR Overrun Indicates a FLAG was generated when the FLAG bit was set to 1 To clear the OVR bit write 1 to cle...

Page 701: ...e shared by the channels through four counter buses and each unified channel can generate its own time base Optionally the counter A bus can be driven by an external time base from the eTPU imported t...

Page 702: ...se imported from the STAC bus to the eMIOS unified channels The eTPU module s time bases and angle count can be exported and or imported through the STAC client submodule interface Time bases and or a...

Page 703: ...e is no freeze function in this submodule 17 4 3 Global Clock Prescaler Submodule GCP The global trace prescaler divides the system clock to generate a clock for the unified channels The system clock...

Page 704: ...events to occur before software intervention is needed Two comparators equal only A and B that compare the selected counter bus with the value in the data registers Internal counter for use as a loca...

Page 705: ...ATE Output disable control bus ODISSL 0 1 EMIOSn EMIOSn Internal bus Unified channel Counter bus select Internal counter Register A1 Register A2 Register B1 Register B2 Notes 1 Counter bus A can be dr...

Page 706: ...s in this signal the 5 bit counter starts counting up As long as the new state is stable on the pin the counter continues incrementing If a counter overflows occurs the new pin value is validated In t...

Page 707: ...y input events that occurs while the channel is frozen are ignored When exiting debug mode or freeze enable bit is cleared FRZ in the EMIOS_MCR or FREN in the EMIOS_CCRn the channel actions resume 17...

Page 708: ...is used as a single output port pin and the value of the EDPOL bit is permanently transferred to the output flip flop NOTE The GPIO modes provided in the eMIOS are particularly useful as interim mode...

Page 709: ...he value in EDPOL is transferred to it At the same time the FLAG bit is set to indicate that the output compare match has occurred Writing to register EMIOS_CADRn stores the value in register A2 and r...

Page 710: ...e measures the width of a positive or negative pulse by capturing the leading edge on register B1 and the trailing edge on register A2 Successive captures are done on consecutive edges of opposite pol...

Page 711: ...reading EMIOS_CADRn forces B1 to be updated with the content of register A1 At the same time transfers between B2 and B1 are disabled until the next read of the EMIOS_CBDRn register Reading EMIOS_CBDR...

Page 712: ...read EMIOS_CBDRn before reading EMIOS_CADRn If B1 register updates are blocked after an EMIOS_CADRn read a second EMIOS_CBDRn read is required to release B1 register updates 17 4 4 4 5 Input Period M...

Page 713: ...Registers EMIOS_CADRn and EMIOS_CBDRn return the values in register A2 and B1 respectively To allow coherent data reading EMIOS_CADRn forces A1 content to be transferred to the B1 register and disable...

Page 714: ...the DAOC mode is first selected coming from GPIO mode both comparators are disabled Comparators A and B are enabled by updating registers A1 and B1 respectively and remain enabled until a match occur...

Page 715: ...th the same value the unified channel behaves as if a single match on comparator B had occurred that is the output flip flop is set to the complement of EDPOL bit and the FLAG bit is set Figure 17 23...

Page 716: ...ectively To guarantee coherent access reading EMIOS_CADRn disables transfers between B2 and B1 These transfers are disabled until the next read of the EMIOS_CBDRn register Reading the EMIOS_CBDRn regi...

Page 717: ...MA and FORCMB bits have no effect when the unified channel is configured for PEA mode Figure 17 25 and Figure 17 26 show how the unified channel can be used for continuous and single shot pulse edge a...

Page 718: ...for the time window After writing to register A1 when a match occur between comparator A and the selected timebase the internal counter is cleared and it is ready to start counting input events When t...

Page 719: ...essed by the alternate address EMIOS_ALTAn For single shot operation MODE 6 set the next match between comparator A and the selected time base has no effect until a new write to register A is performe...

Page 720: ...nd phase_B encoders When operating with count and direction encoder MODE 6 cleared UCn input pin must be connected to the direction signal and UC n 1 input pin must be connected to the count signal of...

Page 721: ...phase_A and phase_B encoders respectively Figure 17 29 Quadrature Decode Mode Example with Count and Direction Encoder Figure 17 30 Quadrature Decode Mode Example with Phase_A and Phase_B Encoder Dire...

Page 722: ...he input signal has the same polarity of EDPOL bit in EMIOS_CCRn and does not count otherwise When a match occurs in comparator B the internal counter is disabled regardless of the input signal polari...

Page 723: ...dulus counter Up down counter no change in counter direction upon match of input counter and register B1 internal clock source 0b0010101 Modulus counter Up down counter no change in counter direction...

Page 724: ...d register A1 sets the FLAG and clears the internal counter When in up down count mode a match between the internal counter and register A1 sets the FLAG and changes the counter direction from increme...

Page 725: ...0 EMIOS_CCNTRn FLAG set event MODE 4 0 A1 match A1 match A1 value1 Notes 1 Writing EMIOS_An writes to A2 A2 value transferred to A1 according to OUn bit Time 0x000000 A1 match A1 match 0x000200 0x0003...

Page 726: ...any time the FORCMA and FORCMB bits allow the software to force the output flip flop to the level corresponding to a match on A or B respectively Also FORCMB clears the internal counter The FLAG bit i...

Page 727: ...eturn to the previous duty cycle restore register A with its former value NOTE Updates to the A register always occur immediately If next period update is selected via the mode 6 bit only the B regist...

Page 728: ...OPWFM with Next Period Update A1 value1 B1 value B2 value2 0x001000 0x000900 Output flip flop A1 match A1 match Time 0x000000 B1 match 0x000200 0x000200 0x001000 0x000900 0x000200 Write to A2 and B2...

Page 729: ...17 25 has additional illustrative examples Table 17 25 Examples of Output Waveforms EDPOL Duty Cycle A decimal B decimal Waveform 0 Active high output 0 1000 1000 25 250 1000 50 500 1000 75 750 1000 1...

Page 730: ...lears the internal counter and switches the selected time base to the internal counter When a match occurs between register B1 and the selected time base the output flip flop is set to the value of th...

Page 731: ...s A1 and B1 must be set to the same value When a simultaneous match occurs between the selected time base and registers A1 and B1 the output flip flop is set at every period to the value of EDPOL bit...

Page 732: ...ead time Insertion Output flip flop A1 match A1 match Time 0x000000 0x000303 0x000200 Update to A1 Selected MODE 6 1 counter bus A1 match Notes 1 Writing EMIOS_An writes to A1 2 Writing EMIOS_Bn write...

Page 733: ...ion FLAG set at match of internal counter and comparator B next period update 0b0100010 Output pulse width modulation FLAG set at match of internal counter and comparator A or comparator B immediate u...

Page 734: ...e FORCMA and FORCMB bits allow the software to force the output flip flop to the level corresponding to a match on A or B respectively The FLAG bit is not set by the FORCMA and FORCMB operations If su...

Page 735: ...900 Update to A1 0xxxxxxx 0x000200 Update to A1 0x001000 Selected MODE 6 0 counter bus A1 match B1 match 0xxxxxxx 0xxxxxxx 0x001000 Notes 1 Writing EMIOS_An writes to A2 2 Writing EMIOS_Bn writes to B...

Page 736: ...internal counter starts counting up from its current value to until an A1 match occurs On the next system clock cycle after an A1 match occurs the internal counter is set to one and the counter contin...

Page 737: ...wn counter mode The A1 register is updated at the cycle boundary If A2 is written in cycle n this new value is used in cycle n 1 for the next A1 match Flags are generated only at an A1 match if MODE 5...

Page 738: ...e n to be used in cycle n 1 Thus A1 receives the new value at the next cycle boundary The EMIOS_OUDR n bits can be used to disable the update of A1 register Figure 17 43 eMIOS MCB Mode Example Up Down...

Page 739: ...anges from 1 up to B1 value When a match on comparator A occurs the output register is set to the value of EDPOL When a match on comparator B occurs the output register is set to the complement of EDP...

Page 740: ...17 44 eMIOS OPWFMB Mode Example A1 B1 Match to Output Register Delay 8 1 4 A1 match 5 A1 value 0x000004 A1 match A1 match negative Output flip flop EMIOS_CCNTRn Time B1 match B1 match B1 match negati...

Page 741: ...me time as the B1 match negative edge from cycle n This allows the use of the A1 match positive edge to mask the B1 match negative edge when they occur at the same time The result is that no transitio...

Page 742: ...A2 instead of A1 for matches if A2 is either 0 or 1 thus allowing matches to be generated even when A1 is being loaded This approach allows a uniform channel operation for any A2 value including 1 and...

Page 743: ...itions at the following A1 or B1 match In Figure 17 47 it is assumed that the output disable input is enabled and selected for the channel refer to Section 17 3 1 7 eMIOS Channel Control Register EMIO...

Page 744: ...leading or trailing edge A1 and B1 registers are double buffered to allow smooth output signal generation when changing A2 or B2 values asynchronously The selected counter bus for a channel configure...

Page 745: ...o generate matches in cycle n 1 Figure 17 49 eMIOS OPWMCB Mode Example A1 B1 Register Loading The EMIOS_OUDR n bit can be used to disable the A1 and B1 updates thus allowing the loading of these regis...

Page 746: ...y cycle and dead time values to be changed at simultaneously Figure 17 50 eMIOS PWMCB Mode Example Lead Dead Time Insertion EDPOL 1 Internal Internal counter is Dead time A1 Value A2 Value B1 Value B2...

Page 747: ...th edges when MODE 5 is set If subsequent matches occur on A and B the PWM pulses continue to be generated regardless of the state of the FLAG bit NOTE In OPWMCB mode FORCMA and FORCMB do not have the...

Page 748: ...dence over FORCMA when trailing dead time insertion is selected Duty cycles from 0 to 100 can be generated by setting appropriate A1 and B1 values relative to the period of the external time base Sett...

Page 749: ...channel matches continue to occur in this case thus generating flags When the output disable is negated the channel output flip flop is again controlled by A1 and B1 matches This process is synchronou...

Page 750: ...rated at B1 matches when MODE 5 is cleared or on both A1 and B1 matches when MODE 5 is set If subsequent matches occur on comparators A and B the PWM pulses continue to be generated regardless of the...

Page 751: ...and B1 match signals Figure 17 53 shows the value of A1 being set to zero in cycle n 1 In this case the match positive edge is used instead of the negative edge to transition the output flip flop 1 4...

Page 752: ...sing the output flip flop to remain at the EDPOL value thus generating a 0 duty cycle Figure 17 54 eMIOS OPWMB Mode Example 0 Duty Cycle 1 4 A1 match negative A1 value 0x000004 A1 match Output flip fl...

Page 753: ...igure 17 56 if B1 is set to a value lower than 0x000008 it is not possible to achieve 0 duty cycle by only changing A1 register value Since B1 matches have precedence over A1 matches the output flip f...

Page 754: ...se output signals To guarantee that the internal counters of correlated channels are incremented in the same clock cycle the internal prescalers must be set up before enabling the global prescaler If...

Page 755: ...efore the prescaled clock remains high and continuously enables the internal counter EMIOS_CCNTRn Figure 17 57 eMIOS Time Base Generation Block Diagram Figure 17 58 shows the prescaler ratio equal to...

Page 756: ...17 60 Time Base Generation Using the Internal Clock with Clear on Match Start Prescaled clock Internal counter 1 2 0 3 Clock 3 1 2 3 0 1 2 EMIOS_CCNTRn Ratio 3 Match value 3 Initial time base period d...

Page 757: ...Enhanced Modular Input Output Subsystem eMIOS MPC5566 Microcontroller Reference Manual Rev 2 17 78 Freescale Semiconductor...

Page 758: ...n rate of the eTPU engine reduces service time Because responding to hardware service requests is primarily done by the eTPU engine the host is free to handle higher level operations 18 1 1 eTPU Imple...

Page 759: ...ell as in the Enhanced Time Processing eTPU Reference Manual 18 1 2 Block Diagram Figure 18 1 shows a top level block diagram of dual eTPU engines in the MPC5566 Figure 18 1 Dual eTPU Block Diagram eT...

Page 760: ...service request The service request microcode can send an interrupt to the device core but cannot directly interrupt the core using I O channel events Each channel has a function that consists of a se...

Page 761: ...a system clock to give absolute time control or by an asyncronous counter such as an angle clock that is tracking the angle of a rotating shaft Each eTPU engine consists of the following blocks 32 ind...

Page 762: ...or angle counter for either match or capture operation For example a match on TCR1 can capture the value of TCR2 The channels can request service from the microengine due to recognized pin transitions...

Page 763: ...access the SDM space mirrored in an alternate area with parameter sign extension PSE PSE allows accessing 24 bit data as 32 bit sign extended data without using the device s bandwidth to extend the da...

Page 764: ...nels needing service and grant execution time to each channel The time given to an individual thread for execution or service is called a time slot The duration of a time slot is determined by the num...

Page 765: ...configuration and control code contributing to reduced service time 18 1 4 7 Dual eTPU Engine System The MPC5566 eTPU implementation includes two eTPU engines sharing SDM and the same code in the SCM...

Page 766: ...rnatively be used as a pulse accumulator gated by an external signal Either time base can be written or read by either eTPU engine at any time Either time base can be read but not written by the host...

Page 767: ...ther begins to service a request from another channel Channel specific registers flags and parameter base address are automatically loaded for the next serviced channel Individual channel priority set...

Page 768: ...saving power Input sampling stops eTPU engines can be in stop mode independently Module disable mode stops only the engine clock so that the shared BIU and global channel registers can be accessed and...

Page 769: ...This serialization is performed by DSPI B Finally some channels are serialized through different DSPIs The eTPU channel 17 is serialized through DSPI B to input 1 on IMUX for external IRQ 6 but is als...

Page 770: ...Output Disable Signals Each eTPU engine has four input signals that are used to force the outputs of a group of eight channels to an inactive level These signals originate from the eMIOS When an outpu...

Page 771: ...24 31 Table 18 4 eTPU High Level Memory Map Address Register Description Base C3FC_0000 Base 0x0000_001F eTPU system module configuration registers Base 0x0000_0020 0x0000_002F eTPU A time base regis...

Page 772: ...MPR eTPU MISC compare register 32 Base 0x0000_0010 ETPU_SCMOFFDATAR eTPU SCM off range data register 32 Base 0x0000_0014 ETPU_ECR_A eTPU A engine configuration register 32 Base 0x0000_0018 ETPU_ECR_B1...

Page 773: ...tus register 32 Base 0x0000_0238 Reserved Base 0x0000_023C Reserved Base 0x0000_0240 ETPU_CIER_A eTPU A channel interrupt enable register 32 Base 0x0000_0244 ETPU_CIER_B1 eTPU B channel interrupt enab...

Page 774: ...Reserved Base 0x0000_0800 ETPU_C0CR_B1 eTPU B channel 0 configuration register 32 Base 0x0000_0804 ETPU_C0SCR_B1 eTPU B channel 0 status and control register 32 Base 0x0000_0808 ETPU_C0HSRR_B1 eTPU B...

Page 775: ...SCM can only be written in 32 bit accesses Address Base 0x0000_0000 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 MGEA MGEB ILFA ILFB 0 0 0 SCMSIZE W GEC Reset 0 0 0 0 0 0 0 0 0 0 0 SCMS...

Page 776: ...s decoded in engine B This bit is cleared by host writing 1 to GEC For more details refer to the eTPU Reference Manual 0 Illegal Instruction not detected 1 Illegal Instruction detected by eTPU B 8 10...

Page 777: ...used 26 30 Reserved 31 GTBE Global time base enable Enables time bases in both engines allowing them to be started synchronously An assertion of GTBE also starts the eMIOS time base1 This enables the...

Page 778: ...r width selection Selects the width of the parameters to be transferred between the PB and the target address 0 Transfer 24 bit parameters The upper byte remains unchanged in the destination address 1...

Page 779: ...resses either by the host or by the microengine This register can be written by the host with the 32 bit instruction to be executed by the microengine to recover from runaway code This register is glo...

Page 780: ...0 21 22 23 24 25 26 27 28 29 30 31 R ETPUSCMOFFDATAR 16 31 W Reset 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 Figure 18 8 eTPU SCM Off Range Data Register ETPU_SCMOFFDATAR Table 18 9 ETPU_SCMOFFDATAR Field Descr...

Page 781: ...PU stops when the thread is complete 0 eTPU engine runs 1 Commands engine to stop its clocks Stop completes on the next system clock after the stop condition is valid The MDIS bit is write protected w...

Page 782: ...eTPU Reference Manual Changing CDFC during eTPU normal input channel operation is not recommended since it changes the behavior of the transition detection logic while executing its operation Table 18...

Page 783: ...crocode entry table for the eTPU functions in SCM More information about entry points is located in the eTPU Reference Manual The following table shows the entry table base address options 1 The time...

Page 784: ...as two eTPU engines each with a dedicated TCRCLK signal TCRCLKA and TCRCLKB Address Base 0x0000_0020 eTPU A Address Base 0x0000_0040 eTPU B Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R TCR2CTL T...

Page 785: ...in integrator mode or two sample mode The following table describes TCRCLK filter clock mode For more information refer to the eTPU Reference Manual 5 Reserved TCR2CTL AM 0 TCR2 Clock AM 1 Angle Toot...

Page 786: ...ing frequency divisions from 1 to 64 The prescaler input is the system clock divided by 8 in gated or non gated clock mode or Internal Timebase input or TCRCLK filtered input This field has no effect...

Page 787: ...n set in ETPU_REDCR For more information refer to the eTPU Reference Manual Address Base 0x0000_0024 eTPU A Address Base 0x0000_0044 eTPU B Access R O 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0...

Page 788: ...de and STAC interface configurations set in registers ETPU_TBCR and ETPU_REDCR For more information on time bases refer to the eTPU Reference Manual Address Base 0x0000_0028 eTPU A Address Base 0x0000...

Page 789: ...or resource 1 is disabled 1 Server client operation for resource 1 is enabled 1 RSC1 TCR1 resource server client assignment Selects the eTPU data resource assignment to be used as a server or client R...

Page 790: ...assignment Selects the eTPU data resource assignment to be used as a server or client RSC2 selects the functionality of TCR2 For server mode external plugging determines the unique server address ass...

Page 791: ...TRSn cleared by writing a 1 to the appropriate field Address Base 0x0000_0200 eTPU A Address Base 0x0000_0204 eTPU B Access R W1c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CIS31 CIS30 CIS29 CIS28 CIS27...

Page 792: ...2 3 4 5 6 7 8 9 10 11 12 13 14 15 R DTRS 31 DTRS 30 DTRS 29 DTRS 28 DTRS 27 DTRS 26 DTRS 25 DTRS 24 DTRS 23 DTRS 22 DTRS 21 DTRS 20 DTRS 19 DTRS 18 DTRS 17 DTRS 16 W w1c w1c w1c w1c w1c w1c w1c w1c w...

Page 793: ...R CIOS 31 CIOS 30 CIOS 29 CIOS 28 CIOS 27 CIOS 26 CIOS 25 CIOS 24 CIOS 23 CIOS 22 CIOS 21 CIOS 20 CIOS 19 CIOS 18 CIOS 17 CIOS 16 W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c Res...

Page 794: ...OS19 DTR OS18 DTR OS17 DTR OS16 W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R DTR OS15 DTR...

Page 795: ...E 13 CIE 12 CIE 11 CIE 10 CIE 9 CIE 8 CIE 7 CIE 6 CIE 5 CIE 4 CIE 3 CIE 2 CIE 1 CIE 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 18 18 eTPU Channel Interrupt Enable Register ETPU_CIER Table 18 19...

Page 796: ...nsfer request disabled for channel n 1 Data transfer request enabled for channel n For details about interrupts refer to the eTPU Reference Manual Address Base 0x0000_0280 eTPU A Address Base 0x0000_0...

Page 797: ...egister since the CHAN register can be changed by the service thread microcode 18 4 6 Channel Configuration and Control Registers Each channel for both eTPU engines has a group of three registers used...

Page 798: ...cted to the DMA controller are left disconnected and do not generate interrupt requests even if their request status bits assert in registers ETPU_CDTRSR and ETPU_CnSCR 0x0008 eTPU channel host servic...

Page 799: ...0 0 0 0 0 0 0 0 0 0 1 ETPD is not available on the MPC5566 Figure 18 22 ETPU Channel n Configuration Register ETPU_CnCR Table 18 25 ETPU_CnCR Field Descriptions Field Description 0 CIE Channel interr...

Page 800: ...formed by the channel The function assigned to the channel has to be compatible with the channel condition encoding scheme selected by ETPU_CnCR ETCS For more information about functions refer to the...

Page 801: ...0 CIS Channel interrupt status 0 Channel has no pending interrupt to the device core 1 Channel has a pending interrupt to the device core CIS is mirrored in the ETPU_CISR For more information on ETPU...

Page 802: ...ate 17 OPS Channel output pin state Shows the current value driven in the channel output signal including the effect of the external output disable feature If the channel input and output signals are...

Page 803: ...addition initialize the SCM with the eTPU application prior to configuring the eTPU Table 18 27 ETPU_CnHSRR Field Descriptions Field Description 0 28 Reserved 29 31 HSR 0 2 Host service request Used b...

Page 804: ...queued analog to digital converter eQADC provides accurate and fast conversions for a wide range of applications The eQADC provides a parallel interface to two on chip analog to digital converters AD...

Page 805: ...so monitors the amount of memory currently in use by each the CFIFO and RFIFO to detect underflow and overflow conditions Command buffer 0 AN 8 _ANW AN 9 _ANX AN 10 _ANY AN 11 _ANZ AN 12 39 REFBYPC AN...

Page 806: ...Os and with the RFIFOs via the result format and calibration submodule The ADC control logic performs the following functions Buffers command data for execution Decodes command data and accordingly ge...

Page 807: ...conversion results Optional automatic application of ADC calibration constants provision of reference voltages 25 VREF 1 and 75 VREF for ADC calibration purposes 40 input channels available to the two...

Page 808: ...st is detected there are commands in the ADC that were already under execution these commands are completed but the generated results if any are not sent to the RFIFOs until debug mode is exited Comma...

Page 809: ...tic stable state from which it can recover when returning to normal mode The eQADC then asserts an acknowledge signal indicating that it is static and that the clock input can be stopped In stop mode...

Page 810: ...ous serial transmission are transmitted only after stop mode exits Command null message transfer through serial interface was aborted but next serial transmission did not start If the stop mode entry...

Page 811: ...I AN 12 Analog Digital Digital 496 416 AN 13 _ MA 1 _ SDO Single ended analog input 13 Mux address 1 eQADC SSI serial data out I O O I AN 13 Analog Digital Digital 496 416 AN 14 _ MA 2 _ SDI Single en...

Page 812: ...O Up Up Digital 496 416 Power Supplies VRH Voltage reference high I VRH Power 496 416 VRL Voltage reference low I VRL Power 496 416 REFBYPC Reference bypass capacitor input I REFBYPC Power 496 416 VDD...

Page 813: ...pop register 1 32 1 Base 0x0038 EQADC_RFPR2 eQADC result FIFO pop register 2 32 1 Base 0x003C EQADC_RFPR3 eQADC result FIFO pop register 3 32 1 Base 0x0040 EQADC_RFPR4 eQADC result FIFO pop register...

Page 814: ...Base 0x0098 EQADC_CFTCR4 eQADC command FIFO transfer counter register 4 16 Base 0x009A EQADC_CFTCR5 eQADC command FIFO transfer counter register 5 16 Base 0x009C Reserved Base 0x00A0 EQADC_CFSSR0 eQA...

Page 815: ...ved Base 0x0300 0x030C EQADC_RF0Rn eQADC RFIFO0 registers 0 3 32 Base 0x0310 0x033C Reserved Base 0x0340 0x034C EQADC_RF1Rn eQADC RFIFO1 registers 0 3 32 Base 0x0350 0x037C Reserved Base 0x0380 0x038C...

Page 816: ...7 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 ESSIE 0 DBG W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19 2 eQADC Module Configuration Register EQADC_MCR Table 19 3 EQADC_MCR F...

Page 817: ...e recognized as an edge or level gated trigger The digital filter length field specifies the Address Base 0x0008 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 NMF W Reset 0 0 0 0 0 0...

Page 818: ...imum number of system clocks that must be counted by the digital filter counter to recognize a logic state change The count specifies the sample period of the digital filter which is calculated accord...

Page 819: ...20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W CF_PUSHn Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19 5 eQADC CFIFO Push Registers 0 5 EQADC_CFPRn Table 19 7 EQADC_CFPRn Fie...

Page 820: ...03C EQADC_RFPR3 Base 0x0040 EQADC_RFPR4 Base 0x0044 EQADC_RFPR5 Access RO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20...

Page 821: ...Writing a 1 to CFINVn resets the value of CFCTRn in the EQADC_FISR register refer to Section 19 3 2 8 eQADC FIFO and Interrupt Status Registers 0 5 EQADC_FISRn Writing a 1 to CFINVn also resets the p...

Page 822: ...ntinuous scan 0b1010 Low level gated external trigger continuous scan 0b1011 High level gated external trigger continuous scan 0b1100 Falling edge external trigger continuous scan 0b1101 Rising edge e...

Page 823: ...EOQFn in EQADC_FISRn is asserted Refer to Section 19 3 2 8 eQADC FIFO and Interrupt Status Registers 0 5 EQADC_FISRn 0 Disable end of queue interrupt request 1 Enable end of queue interrupt request 4...

Page 824: ...s 0 Disable overflow interrupt request 1 Enable overflow Interrupt request 13 Reserved 14 RFDEn RFIFO drain enable n Enables the eQADC to generate an interrupt request RFDSn is asserted or eDMA reques...

Page 825: ...9 4 3 6 5 Command Sequence Non Coherency Detection 0 Command sequence being transferred by CFIFOn is coherent 1 Command sequence being transferred by CFIFOn became non coherent Note Non coherency mean...

Page 826: ...ith asserted pause bit was transferred from CFIFOn CFIFO in edge trigger mode or CFIFO status changes from the TRIGGERED state due to detection of a closed gate CFIFO in level trigger mode Note In edg...

Page 827: ...details The SSSn bit is set by writing a 1 to the SSEn bit see Section Section 19 3 2 6 eQADC CFIFO Control Registers 0 5 EQADC_CFCRn The eQADC clears the SSSn bit when a command with an asserted EOQ...

Page 828: ...st one valid entry Note In the interrupt service routine RFDF must be cleared only after the RFIFOn pop register is read Note RFDFn should not be cleared when RFDSn is asserted eDMA requests selected...

Page 829: ...s has no effect Address EQADC_BASE 0x0090 EQADC_CFTCR0 EQADC_BASE 0x0092 EQADC_CFTCR1 EQADC_BASE 0x0094 EQADC_CFTCR2 EQADC_BASE 0x0096 EQADC_CFTCR3 EQADC_BASE 0x0098 EQADC_CFTCR4 EQADC_BASE 0x009A EQA...

Page 830: ...12 16 Reserved 17 20 LCFT0 0 3 Last CFIFO to transfer to ADCn command buffer Holds the CFIFO number of last CFIFO to have initiated a command transfer to ADCn command buffer LCFT0 has the following v...

Page 831: ...0 3 Last CFIFO to transfer to ADCn command buffer Holds the CFIFO number of last CFIFO to have initiated a command transfer to ADCn command buffer LCFT1 has the following values 21 31 TC_LCFT1 0 10 Tr...

Page 832: ...CFIFO Status Snapshot Register 2 EQADC_CFSSR2 Table 19 16 EQADC_CFSSR2 Field Descriptions Field Description 0 11 CFSn_TSSI 0 1 CFIFO Status at Transfer through the eQADC SSI Indicates the CFIFOn stat...

Page 833: ...LCFTSSI is a copy of the corresponding TC_CFn in EQADC_CFTCRn see Section 19 3 2 9 eQADC CFIFO Transfer Counter Registers 0 5 EQADC_CFTCRn captured at the time a command transfer to an external comman...

Page 834: ...ransfer of the last entry of the user defined command queue in single scan mode Reserved 0b01 Not applicable WAITING FOR TRIGGER 0b10 CFIFO mode is modified to continuous scan edge or level trigger mo...

Page 835: ...are disabled Refer to EQADC_MCR ESSIE field in Section 19 3 2 1 eQADC Module Configuration Register EQADC_MCR 24 27 Reserved 28 31 BR 0 3 Baud rate Selects system clock divide factor as shown in Table...

Page 836: ...1 1 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R R_DATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19 16 eQADC SSI Receive Data Register EQADC_SSIRDR Table 19 22 EQADC_SSIRDR Field Descr...

Page 837: ...e 0x0180 CF2R0 Base 0x0184 CF2R1 Base 0x0188 CF2R2 Base 0x018C CF2R3 Access RO CFIFO3 Base 0x01C0 CF3R0 Base 0x01C4 CF3R1 Base 0x01C8 CF3R2 Base 0x01CC CF3R3 CFIFO4 Base 0x0200 CF4R0 Base 0x0204 CF4R1...

Page 838: ...F2R0 Base 0x0384 RF2R1 Base 0x0388 RF2R2 Base 0x038C RF2R3 Access RO RFIFO3 Base 0x03C0 RF3R0 Base 0x03C4 RF3R1 Base 0x03C8 RF3R2 Base 0x03CC RF3R3 RFIFO4 Base 0x0400 RF4R0 Base 0x0404 RF4R1 Base 0x04...

Page 839: ...configuration commands sent to the ADC1 command buffer Registers ADC_TSCR and ADC_TBCR can be accessed by configuration commands sent to the ADC0 command buffer or to the ADC1 command buffer A data wr...

Page 840: ...0 ADC0_CLK_PS W Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R ADC1 _EN 0 0 0 ADC1_ EMUX 0 0 0 0 0 0 ADC1_CLK_PS W Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 Figur...

Page 841: ...only be written when the ADCn_EN bit is negated ADCn_EMUX can be set during the same write cycle used to set ADCn_EN 5 10 Reserved 11 15 ADCn_ CLK_PS 0 4 ADCn clock prescaler The ADCn_CLK_PS field co...

Page 842: ...onfiguration command sent to ADC0 writes to the same memory location as a write using a configuration command sent to ADC1 NOTE Simultaneous write accesses from ADC0 and ADC1 to ADC_TSCR are not allow...

Page 843: ...writes the same memory location as a write using a configuration command sent to ADC1 Table 19 29 ADC_TSCR Field Descriptions Field Description 0 11 Reserved 12 15 TBC_ CLK_PS 0 3 Time base counter cl...

Page 844: ...15 R TBC_VALUE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19 21 ADC Time Base Counter Register ADC_TBCR Table 19 31 ADC_TBCR Field Descriptions Field Description 0 15 TBC_ VALUE 0 15 Time base cou...

Page 845: ...sts generated by the eQADC The eQADC supports software and Table 19 32 ADCn_GCCR Field Descriptions Field Description 0 Reserved 1 15 GCCn 0 14 ADCn gain calibration constant GCC1 is an unsigned 15 bi...

Page 846: ...nterrupt and eDMA requests generated by the eQADC The eQADC generates these requests whenever a CFIFO is not full The FIFO control unit transfers only the command part of the command message to the AD...

Page 847: ...enever an RFIFO has at least one entry NOTE While conversion results are returned the eQADC is checking the number of entries in the RFIFO and generating requests to empty it The process of pushing an...

Page 848: ...command buffer must have the ABORT_ST bit negated see Section Command Message Format for External Device Operation 19 4 1 1 2 Number of Command Buffers and Result Buffers The external device should ha...

Page 849: ...to the latest information on the fullness state of the command buffers For example if external command buffer 2 is empty before the end of the current serial transmission and if at the end of this tr...

Page 850: ...ed that the device returns an RFIFO header in the format expected by the eQADC When the FIFO control unit receives return data message it decodes the message tag field and stores the 16 bit data into...

Page 851: ...ue When the eQADC completes the transfer of a command with an asserted pause bit the CFIFO enters the WAITING FOR TRIGGER state Refer to Section 19 4 3 6 1 CFIFO Operation Status for a description of...

Page 852: ...ure for details 0 Return conversion result only 1 Return conversion time stamp after the conversion result 15 FMT Conversion data format FMT specifies to the eQADC how to format the 12 bit conversion...

Page 853: ...Configuration Field Description 0 EOQ End of queue Asserted in the last command of a command queue to indicate to the eQADC that a scan of the queue is completed EOQ instructs the eQADC to reset its...

Page 854: ...ending on the EBI bit setting 0 Message buffer 0 1 Message buffer 1 7 R W Read write A negated R W indicates a write configuration command 0 Write 1 Read 8 15 ADC_ REGISTER _HIGH_ BYTE 0 7 ADC registe...

Page 855: ...eue When the eQADC completes the transfer of a command with an asserted pause bit the CFIFO enters the WAITING FOR TRIGGER state Refer to Section 19 4 3 6 1 CFIFO Operation Status for a description of...

Page 856: ...left shift on the 12 bit data received from the ADC When the CAL bit is asserted 8 11 MESSAGE _TAG 0 3 MESSAGE_TAG field Allows the eQADC to separate returning results into different RFIFOs When the...

Page 857: ...9 10 11 12 13 14 15 SIGN_EXT CONVERSION_RESULT With inverted MSB bit 0 0 ADC Result Figure 19 29 ADC Result Format when FMT 1 Right Justified Signed On Chip ADC Operation Table 19 37 ADC Result Format...

Page 858: ...device to which the command and the external command buffer is sent The remaining 25 bits can be anything decodable by the external device Only the ADC command portion of a command message is transfer...

Page 859: ...atus for a description of the state transitions The pause bit is only valid when CFIFO operation mode is configured to single or continuous scan edge trigger mode 0 Do not enter WAITING FOR TRIGGER st...

Page 860: ...ult Figure 19 32 Result Message Format for External Device Operation Table 19 41 Result Message Format for External Device Operation Field Description 6 7 Reserved 8 11 MESSAGE _TAG 0 3 MESSAGE_TAG Fi...

Page 861: ...ers a null message it directly shifts out the 26 bit data content inside the Section 19 3 2 2 eQADC Null Message Send Format Register EQADC_NMSFR The register must be programmed with the null message...

Page 862: ...19 4 3 1 CFIFO Basic Functionality There are six prioritized CFIFOs located in the eQADC Each CFIFO is four entries deep and each CFIFO entry is 32 bits long A CFIFO serves as a temporary storage loc...

Page 863: ...ta pointer and CFCTR in the same register provides the number of entries stored in the CFIFO Using TNXTPTR and CFCTR the absolute addresses for the entries indicated by the transfer next data pointer...

Page 864: ...unter value and does not overwrite any entry in CFIFOn Figure 19 35 CFIFO Diagram The detailed behavior of the push next data pointer and transfer next data pointer is described in the example shown i...

Page 865: ...command buffer that is not full and it is the highest priority triggered CFIFO sending commands to that buffer First In Transfer Next Data Pointer Last In Push Next Data Pointer CFIFOn Transfer Next...

Page 866: ...are not considered for prioritization No data from these CFIFOs is sent to the on chip ADCs or the external command buffers and lower priority CFIFOs are not stopped from transferring commands Whenev...

Page 867: ...y transmitting null message is not shifted out The command from the CFIFO is then written into eQADC SSI transmit buffer allowing for a new serial transmission to initiate In case a command is being t...

Page 868: ...ad that command and start its transmission However if the previously scheduled data was a command no rescheduling occurs and the next transmission starts without delays If a CFIFO becomes triggered wh...

Page 869: ...counter is cleared and restarted each time the signal transitions between logic levels When the corresponding counter matches the value specified by the digital filter length field in Section 19 3 2...

Page 870: ...is scanned multiple times The eQADC also supports different triggering mechanisms for each scan mode The eQADC does not transfer commands from a CFIFO until the CFIFO is triggered The combination of s...

Page 871: ...invalidated by writing a 1 to the CFINVn bit see Section 19 3 2 6 eQADC CFIFO Control Registers 0 5 EQADC_CFCRn Certify that CFS has changed to IDLE before setting CFINVn The TC_CFn value also is not...

Page 872: ...e triggered mode is selected for a CFIFO an appropriate edge on the associated trigger signal causes the CFIFO to become triggered For example if rising edge trigger mode is selected the CFIFO becomes...

Page 873: ...EQADC_CFCRn SSE see Section 19 3 2 6 eQADC CFIFO Control Registers 0 5 EQADC_CFCRn does not have any effect Continuous Scan Software Trigger When a CFIFO is programmed to continuous scan software tri...

Page 874: ...CF counter is updated the PF flag is asserted and the CFIFO status is changed to waiting for trigger Command transfers restart as the gate opens If the gate closes and opens during the same serial tra...

Page 875: ...Level No Gate is opened No No The eQADC also stops transfers from the CFIFO when CFIFO status changes from triggered due to the detection of a closed gate 5 1 Refer to Section 19 4 3 6 2 Command Queu...

Page 876: ...GGER 0b10 CFIFO mode is programmed to continuous scan edge or level trigger mode OR CFIFO mode is programmed to single scan edge or level trigger mode and SSS is asserted OR CFIFO mode is programmed t...

Page 877: ...ed to disabled OR CFIFO in single scan level trigger mode and the gate closes while no commands are being transferred from the CFIFO and CFIFO mode is not modified to disabled OR CFIFO in single scan...

Page 878: ...errupt Status Registers 0 5 EQADC_FISRn Section 19 3 2 8 eQADC FIFO and Interrupt Status Registers 0 5 EQADC_FISRn Section 19 4 1 2 Message Format in eQADC for information on command message formats I...

Page 879: ...5 Command Sequence Non Coherency Detection The eQADC provides a mechanism to indicate if a command sequence has been completely executed without interruptions A command sequence is defined as a group...

Page 880: ...ommands are transferred by a CFIFO configured for edge trigger mode and the command transfers are never interrupted the eQADC checks for non coherency of two command sequences one formed by commands 0...

Page 881: ...command buffer is considered empty when the corresponding BUSY field in the last result message received from external device is encoded as Send available commands buffer is empty Refer to Section Res...

Page 882: ...nce After command transfers restart or continue the non coherency hardware operate as if the command sequence started from that point Figure 19 45 depicts how the non coherency hardware operates when...

Page 883: ...mands to be sent to ADC1 and both are not triggered a CFIFO5 CF5_ADC1_CM3 3 CF5_ADC1_CM2 2 Sent 1 Sent 0 TNXTPTR ADC1 CF5_ADC1_CM1 1 CF5_ADC1_CM0 0 CFIFO5 becomes triggered and transfers CFIFO0 CF0_AD...

Page 884: ...xternal CFIFO0 CF0_2_CM3 3 CF0_2_CM2 2 Sent 1 Sent 0 TNXTPTR command buffer 2 CFIFO5 cannot send commands to external command buffer 3 because the eQADC SSI is b Command Buffer 3 CF5_3_CM1 1 Empty 0 e...

Page 885: ...FIFO Pop Registers 0 5 EQADC_RFPRn to retrieve data from the RFIFO NOTE Reading a word halfword or any bytes from EQADC_RFPRn pops an entry from RFIFOn and the RFCTRn field decrements by 1 Configure t...

Page 886: ...n When a new message arrives and RFIFOn is not full the eQADC copies its contents into the entry pointed by receive next data pointer The RFIFO counter EQADC_FISRn RFCTRn see Section 19 3 2 8 eQADC FI...

Page 887: ...e actual hardware implementation has only four entries In this example RFIFOn with 16 entries is shown in sequence after popping or receiving entries Pop Next Data Entry 1 Data Entry 2 Control Signals...

Page 888: ...umber or Ignores the data in case of a null or reserved for customer use MESSAGE_TAG First In Pop Next Data Pointer Last In Receive Next Data Pointer RFIFOn Pop Next Data Pointer Receive Next Data Poi...

Page 889: ...e bit is negated After the enable bit of an ADC is asserted clock input is started and the bias generator circuit is turned on When the enable bits of both ADCs are negated the bias circuit generator...

Page 890: ...z and the number of sampling cycles set to its minimum 2 cycles The maximum conversion speed for differential and single ended conversions are 800 k samples sec and 750 k samples sec respectively Tabl...

Page 891: ...4 N A N A N A 0b00010 6 N A N A N A 0b00011 8 N A N A N A 0b00100 10 12 0 800 750 0b00101 12 10 0 667 625 0b00110 14 8 57 571 536 0b00111 16 7 5 500 469 0b01000 18 6 67 444 417 0b01001 20 6 0 400 375...

Page 892: ...ncy it is incremented The time stamps are returned regardless of whether the time base counter is enabled or disabled The time base counter can be reset by writing 0x0000 to the ADC_TBCR Section 19 3...

Page 893: ...ted the result is not calibrated it bypasses the calibration hardware and is directly sent to the appropriate RFIFO 19 4 5 4 2 MAC Unit and Operand Data Format The MAC unit diagram is shown in Figure...

Page 894: ...10 11 12 13 14 15 GCC_INT GCC_FRAC Figure 19 50 Gain Calibration Constant Format Table 19 48 Gain Calibration Constant Format Field Descriptions Field Description 0 Reserved 1 GCC_INT Integer part of...

Page 895: ...can start while in ENTRY0 This is explained below A D conversion accuracy can be affected by the settling time of the input channel multiplexers Some time is required for the channel multiplexer s in...

Page 896: ...MA0 MA1 Configuration Registers EMUX0 EMUX1 Entry1 LST0 Entry0 ADC0 Buffer Entry1 LST1 Entry0 ADC1 Buffer Register Data 0 1 CHANNEL_NUMBER0 CHANNEL_NUMBER1 MESSAGE_TAG1 FMT1 CAL1 MESSAGE_TAG0 FMT0 CAL...

Page 897: ...ons can only be initiated on four channels DAN0 DAN1 DAN2 and DAN3 Refer to Table 19 51 and Figure 19 52 for the channel numbers used to select differential conversions MUX Settle Time and Sampling AD...

Page 898: ...analog input pins but simultaneous conversions are not allowed Also when one ADC is performing a differential conversion on a pair of pins the other ADC must not access either of these two pins as si...

Page 899: ...nnel number assignments for the multiplexed mode Only one ADC can have its ADC0 1_EMUX bit asserted at a time Table 19 52 Multiplexed Channel Assignments1 1 The two on chip ADCs can access the same an...

Page 900: ...and ANZ The MA pins correspond to the three least significant bits of the channel number that selects ANW ANX ANY and ANZ with MA 0 being the most significant bit Refer to Table 19 53 When the extern...

Page 901: ...re described in Section 19 3 2 7 eQADC Interrupt and eDMA Control Registers 0 5 EQADC_IDCRn and the interrupt flag bits are described in Section 19 3 2 8 eQADC FIFO and Interrupt Status Registers 0 5...

Page 902: ...CFFFn bit by writing a 1 to the bit Result FIFO Overflow Interrupt 2 2 Apart from generating an independent interrupt request for when a RFIFO overflow interrupt a CFIFO underflow interrupt and a CFI...

Page 903: ...ll DMA Request RFDEn RFDFn RFDSn RFIFO Drain DMA Request DMA Request Generation Logic CFFEn CFFFn CFFSn CFIFO Fill Interrupt Request NCIEn NCFn Non Coherency Interrupt Request PIEn PFn Pause Interrupt...

Page 904: ...ng the EQADC_MCR ESSIE see Section 19 3 2 1 eQADC Module Configuration Register EQADC_MCR When enabled the eQADC SSI can be optionally capable of starting serial transmissions When serial transmission...

Page 905: ...the positive edge of FCK and latches incoming data on the next positive edge of FCK Slave drives data on the positive edge of FCK and latches incoming data on the negative edge of FCK Master initiates...

Page 906: ...K as a clock on the slave device 19 4 8 1 1 Abort Feature The master indicates it is aborting the current transfer by negating SDS before the whole data frame has being shifted out that is the 26th bi...

Page 907: ...Interface Protocol Timing NOTE tMDT Minimum tDT is programmable and defined in Section 18 3 2 12 eQADC SSI Control Register EQADC_SSICR FCK SDS Master Sample Input SDO 1 End Transmission tDT Slave Sam...

Page 908: ...positive edge of FCK Slave drives second bit due to detection of an asserted SDS on the negative edge of FCK 1 FCK SDS Slave Sample Input tDT Master s SDI 26 25 1 2 3 End Transmission Begin Transmissi...

Page 909: ...in Figure 19 60 To begin an analog to digital conversion a differential input is passed into the analog RSD stage The signal is passed through the RSD stage and then from the RSD stage output back to...

Page 910: ...the end of an entire AD conversion cycle the RSD adder uses these collected values to calculate the 12 bit digital output Figure 19 62 shows the transfer function for the RSD stage Note how the digit...

Page 911: ...multiple user command queues Table 19 56 describes how each queue can be used for a different application Also documented in this section are general guidelines on how to initialize the on chip ADCs a...

Page 912: ...o enable the eQADC SSI to start serial transmissions 5 Configure the eDMA to transfer data from Queue0 to CFIFO0 in the eQADC 6 Configure Section 19 3 2 7 eQADC Interrupt and eDMA Control Registers 0...

Page 913: ...eues in the RAM by the eDMA NOTE There is no fixed relationship between CFIFOs and RFIFOs with the same number The results of commands being transferred through CFIFO1 can be returned to any RFIFO reg...

Page 914: ...eue 1 Table 19 57 Example of Command Queue Commands1 1 Fields LST TSR FMT and CHANNEL_NUMBER are not shown for clarity Refer to Section Conversion Command Message Format for On Chip ADC Operation for...

Page 915: ...9 3 2 6 eQADC CFIFO Control Registers 0 5 EQADC_CFCRn Step Four Command transfer to ADCs and result data reception When an external rising edge event occurs for CFIFO1 the eQADC automatically begins t...

Page 916: ...e scan mode Refer to Chapter 9 Enhanced Direct Memory Access eDMA for details about how this functionality is supported 19 5 2 2 Receive Queue RFIFO Transfers In transfers involving receive queues and...

Page 917: ...01 Refer to Section 19 3 2 4 eQADC CFIFO Push Registers 0 5 EQADC_CFPRn 4 Up to 4 commands can be queued in CFIFO5 Check the CFCTR5 status in EQADC_FISR5 before pushing another command to avoid overfl...

Page 918: ...QADC_CFCRn CFINVn see Section 19 3 2 6 eQADC CFIFO Control Registers 0 5 EQADC_CFCRn to invalidate the entries of CFIFOn 7 Configure the eDMA to respond to eDMA requests generated by CFFFn and RFDFn 8...

Page 919: ...e Command 0 No Results 0x0000 CQueue0 Read Command 1 Results to RQueue0 0x0004 CQueue0 Conversion Command 2 Results to RQueue0 0x0008 CQueue0 Conversion Command 3 Results to RQueue1 0x000C CQueue0 Con...

Page 920: ...omatically calibrates the results according to Equation 19 1 of every conversion command that has its CAL bit asserted using the GCC and OCC values stored in the ADC calibration registers 19 5 6 1 MAC...

Page 921: ...e using Equation 19 4 and Equation 19 5 the gain and offset calibration constants are GCC 12288 4096 11592 3798 1 05106492 1 051025391 0x4344 OCC 12288 1 05106492 11592 2 102 06 102 0x0066 Table 19 58...

Page 922: ...ust be familiar with QADC terminology to fully comprehend the following sections Figure 19 69 is an overview of a QADC Figure 19 69 QADC Overview 4 Ideal Transfer Curve 0 Shifted Transfer Curve ADC Tr...

Page 923: ...SSI is implemented to transmit and receive data between the eQADC and the external device Because there are only FIFOs inside the eQADC much of the terminology or use of the register names register co...

Page 924: ...g a pause bit in the CCW pauses the queue execution In the eQADC detecting a pause bit in the command pauses command transfers from a CFIFO Queue Operation Mode MQn CFIFO Operation Mode MODEn The eQAD...

Page 925: ...Enhanced Queued Analog to Digital Converter eQADC MPC5566 Microcontroller Reference Manual Rev 2 19 122 Freescale Semiconductor...

Page 926: ...hich provides a synchronous serial bus for communication between the MCU and an external peripheral device Microcontroller chips in the MPC55xx family implement different DSPI modules Some implement D...

Page 927: ...ical DSPI modules DSPI A DSPI B DSPI C and DSPI D on the device The DSPI has three configurations Serial peripheral interface SPI configuration where the DSPI operates as an SPI with support for queue...

Page 928: ...aster and slave mode Buffered transmit and receive operation using the TX and RX FIFOs with depths of four entries Visibility into TX and RX FIFOs for ease of debugging FIFO bypass mode for low latenc...

Page 929: ...y TFUF Modified SPI transfer formats for communication with slower peripheral devices Supports all functional modes from QSPI subblock of QSMCM MPC500 family Continuous serial communications clock SCK...

Page 930: ...esponds to externally controlled serial transfers The DSPI cannot initiate serial transfers in slave mode In slave mode the SCK signal and the PCSx 0 _SS signal are configured as inputs and provided b...

Page 931: ...he DSPI chip select or slave select primary function is configured for that pin When the pin is used for DSPI master mode as a chip select output set the OBE bit When the pin is used in DSPI slave mod...

Page 932: ...x_MCR is set to 1 the PCSS signal indicates the timing used to decode PCSx 0 4 signals which prevents glitches from occurring PCSx 5 _PCSS is not used in slave mode 20 2 2 5 Serial Input SINx SINx is...

Page 933: ...ibutes register 7 32 Base 0x002C DSPIx_SR DSPI status register 32 Base 0x0030 DSPIx_RSER DSPI DMA interrupt request select and enable register 32 Base 0x0034 DSPIx_PUSHR DSPI push TX FIFO register 32...

Page 934: ...er DSPIx_MCR Table 20 3 DSPIx_MCR Field Descriptions Field Description 0 MSTR Master or slave mode select Configures the DSPI for master mode or slave mode 0 DSPI is in slave mode 1 DSPI is in master...

Page 935: ...uest RFOF 0 Incoming data is ignored 1 Incoming data is put in the shift register 8 9 Reserved but implemented These bits are writable but have no effect 10 15 PCSISn Peripheral chip select inactive s...

Page 936: ...RX FIFO Write a 1 to the CLR_RXF bit to clear the RX counter The CLR_RXF bit is always read as zero 0 Do not clear the RX FIFO counter 1 Clear the RX FIFO counter 22 23 SMPL_ PT 0 1 Sample point Allow...

Page 937: ...inations of transfer attributes such as frame size clock phase and polarity data bit ordering baud rate and various delays In slave mode a subset of the bit fields in the DSPIx_CTAR0 and DSPIx_CTAR1 r...

Page 938: ...ributes are selected based on whether the current frame is SPI data or DSI data SPI transfers in CSI configuration follow the protocol described for SPI configuration and DSI transfers in CSI configur...

Page 939: ...ase bit as listed in the following table See the BR field and Section 20 4 6 1 Baud Rate Generator for details on how to compute the baud rate If the overall baud rate is divided by two or three syste...

Page 940: ...e devices must have identical clock phase settings 0 Data is captured on the leading edge of SCKx and changed on the following edge 1 Data is changed on the leading edge of SCKx and captured on the fo...

Page 941: ...5 details how to compute the delay after transfer 14 15 PBR 0 1 Baud rate prescaler Selects the prescaler value for the baud rate Use in master mode only The baud rate is the frequency of the serial c...

Page 942: ...between the last edge of SCKx and the negation of PCSx The following table lists the scaler values The after SCKx delay is a multiple of the system clock period and it is computed using the following...

Page 943: ...he next frame The following table lists the scaler values The delay after transfer is a multiple of the system clock period It is computed using the following equation Note See Section 20 4 6 4 Delay...

Page 944: ...SCK The following table lists the baud rate scaler values The baud rate is computed using the following equation Note See Section 20 4 6 1 Baud Rate Generator for more details Address Base 0x002C Acc...

Page 945: ...The EOQF bit is cleared by writing 1 to it When the EOQF bit is set the TXRXS bit is automatically cleared 0 EOQ is not set in the executing command 1 EOQ bit is set in the executing SPI command Note...

Page 946: ...nd the SPI data is transferred to the shift register 20 23 TXNXTPTR 0 3 Transmit next pointer Indicates which TX FIFO entry is transmitted during the next transfer The TXNXTPTR field is updated every...

Page 947: ...e Enables the TFFF flag in the DSPIx_SR to generate a request The TFFF_DIRS bit selects between generating an interrupt request or a DMA requests 0 TFFF interrupt requests or DMA requests are disabled...

Page 948: ...or interrupt request select Selects between generating a DMA request or an interrupt request When the RFDF flag bit in the DSPIx_SR is set and the RFDF_RE bit in the DSPIx_RSER is set the RFDF_DIRS b...

Page 949: ...le shows how the CTAS values map to the DSPIx_CTARs There are eight DSPIx_CTARs in the device DSPI implementation Note Use in SPI master mode only 4 EOQ End of queue Provides a means for host software...

Page 950: ...x_POPR only when you need the data For compatibility configure the TLB MMU table entry for DSPIx_POPR as guarded 10 15 PCSx Peripheral chip select x Selects which PCSx signals are asserted for the tra...

Page 951: ...ield Descriptions Field Description 0 15 Reserved must be cleared 16 31 RXDATA 0 15 Received data The RXDATA field contains the SPI data from the RX FIFO entry pointed to by the pop next data pointer...

Page 952: ...e RX FIFO that is DSPIx_RXFR0 DSPIx_RXFR3 are used The following table describes the field in the DSPI receive FIFO register Address Base 0x007C DSPIx_RXFR0 Base 0x0080 DSPIx_RXFR1 Base 0x0084 DSPIx_R...

Page 953: ...on 0 Multiple transfer operation disabled 1 Multiple transfer operation enabled 1 Reserved 2 7 MTOCNT 0 5 Multiple transfer operation count Selects number of bits to be shifted out during a transfer i...

Page 954: ...ble Enables the PCSx signals to remain asserted between transfers The DCONT bit only affects the PCS signals in DSI master mode See Section 20 4 7 5 Continuous Selection Format for details 0 Return pe...

Page 955: ...data The following table describes the field in the DSPI deserial serial interface serialization data register Address Base 0x00C0 Access R O 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0...

Page 956: ...boundary The following table describes the field in the DSPI deserial serial interface alternate serialization data register Address Base 0x00C4 Access R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0...

Page 957: ...owing table describes the field in the DSPI deserial serial interface transmit comparison register Address Base 0x00C8 Access R O 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 958: ...ates as a basic SPI or a queued SPI Deserial serial interface DSI configuration where the DSPI serializes eTPU and eMIOS output channels and deserializes the received data by placing it on the eTPU an...

Page 959: ...hift register is now in the shift register of the slave and vice versa At the end of a transfer the TCF bit in the DSPIx_SR is set to indicate a completed transfer Figure 20 17 illustrates how master...

Page 960: ...configuration transfer attributes and SPI data is transferred using the SPI configuration transfer attributes In order for the bus slave to distinguish between DSI and SPI frames the transfer attribut...

Page 961: ...to in slave mode The STOPPED state is also a safe state for writing the various configuration registers of the DSPI without causing undetermined results The TXRXS bit in the DSPIx_SR is cleared in thi...

Page 962: ...FO operations are similar for the master mode and slave mode The main difference is that in master mode the DSPI initiates and controls the transfer according to the fields in the SPI command field of...

Page 963: ...ds four entries each consisting of a command field and a data field SPI commands and data are added to the TX FIFO by writing to the DSPI push TX FIFO register DSPIx_PUSHR For more information on DSPI...

Page 964: ...the DSPIx_POPR register RX FIFO entries can only be removed from the RX FIFO by reading the DSPIx_POPR or by flushing the RX FIFO See Section 20 3 2 7 DSPI POP RX FIFO Register DSPIx_POPR for more inf...

Page 965: ...e various features of the DSI configuration are set in the DSPIx_DSICR For more information on the DSPIx_DSICR The DSPI is in DSI configuration when the DCONF field in the DSPIx_MCR is 0b01 See Sectio...

Page 966: ...alized using two different sources The TXSS bit in the DSPIx_DSICR selects between the DSPIx_SDR and DSPIx_ASDR as the source of serialized data See Section 20 3 2 11 DSPI DSI Serialization Data Regis...

Page 967: ...n chaining DSPIs the master and all slaves must be configured for the transfer initiation The transfer initiation conditions are selected by the TRRE and CID bits in the DSPIx_DSICR Table 20 18 lists...

Page 968: ...4 4 5 4 Triggered or Change In Data Control For triggered or change in data control initiation of a transfer is controlled by the ht signal or by the detection of a change in data to be serialized 20...

Page 969: ...utput Channel 9 6 6 N C eTPUB Output Channel 8 7 7 N C eTPUB Output Channel 7 8 8 N C eTPUB Output Channel 6 9 9 N C eTPUB Output Channel 5 10 10 N C eTPUB Output Channel 4 11 11 N C eTPUB Output Chan...

Page 970: ...A output channel 17 6 6 Input 1 on IMUX for external IRQ 6 eTPUA output channel 16 7 7 Input 1 on IMUX for external IRQ 7 eTPUA output channel 29 8 8 eTPUA input channel 29 input 1 on IMUX for externa...

Page 971: ...channel 1 5 5 Input 2 on IMUX for external IRQ 4 eTPUA output channel 2 6 6 Input 2 on IMUX for external IRQ 5 eTPUA output channel 3 7 7 Input 2 on IMUX for external IRQ 6 eTPUA output channel 4 8 8...

Page 972: ...ut the slave generates a trigger signal on the MTRIG output The SIU_DISR must be configured to use serial or parallel chaining Table 20 22 DSPI D Connectivity Table Connected to DSPI D IN n DSPI D OUT...

Page 973: ...uts Figure 20 26 DSPI A B C and D Inputs for Multi transfer Operations The source for the SINx input of a DSPI can be a pin or the SOUTx of any of the other three DSPIs The source for the SSx input of...

Page 974: ...ansfers but the DSPI slaves each have a trigger output signal MTRIG that indicates to DSPI A that a trigger condition has occurred in the DSPI slaves When the slave DSPI has a change in data to be ser...

Page 975: ...o be serialized it can assert the MTRIG signal to the DSPI master which initiates the transfer When a DSPI slave has its ht signal asserted its MTRIG signal asserts and propagates trigger signals from...

Page 976: ...rol When there are SPI commands in the TX FIFO the SPI data has priority over the DSI frames When the TX FIFO is empty DSI transfer resumes Two peripheral chip select signals indicate whether DSI data...

Page 977: ...ion 20 3 2 11 DSPI DSI Serialization Data Register DSPIx_SDR 20 4 5 2 CSI Deserialization The deserialized frames in CSI configuration go into the DSPIx_SDR or the RX FIFO based on the transfer priori...

Page 978: ...lds in the DSPIx_CTARs select the frequency of SCKx using the following formula Table 20 23 shows an example of a computed baud rate 20 4 6 2 PCS to SCK Delay tCSC The PCSx to SCKx delay is the length...

Page 979: ...SPIx_CTARn registers select the delay after transfer See Figure 20 34 for an illustration of the delay after transfer The following formula expresses the PDT and DT delay after transfer relationship T...

Page 980: ...ication is controlled by the serial communications clock SCKx signal and the PCSx signals The SCKx signal provided by the master device synchronizes shifting and sampling of the data by the SINx and S...

Page 981: ...s high speed communication with peripherals that require longer setup times The DSPI can sample the incoming data later than halfway through the cycle to give the peripheral more setup time The MTFE b...

Page 982: ...ial data output signals For the rest of the frame the master and the slave sample their SINx pins on the odd numbered clock edges and changes the data on their SOUTx pins on the even numbered clock ed...

Page 983: ...ster and slave sample their SINx pins For the rest of the frame the master and the slave change the data on their SOUTx pins on the odd numbered clock edges and sample their SINx pins on the even numb...

Page 984: ...ta to the SOUTx pins when the PCSx signal asserts After the PCSx to SCKx delay elapses the first SCKx edge is generated The slave samples the master SOUTx signal on every odd numbered SCKx edge The sl...

Page 985: ...lave put data on their SOUT pins at the first edge of SCK The slave samples the master SOUT signal on the even numbered edges of SCK The master samples the slave SOUT signal on the odd numbered SCK ed...

Page 986: ...vides the flexibility to handle both cases The continuous selection format is enabled for the SPI configuration by setting the CONT bit in the SPI command Continuous selection is enabled for the DSI c...

Page 987: ...the period length at the start of the next transfer is the sum of tASC and tCSC i e it does not include a half clock period The default settings for these provide a total of four system clocks In man...

Page 988: ...ontinuous SCK is supported for modified transfer format Clock and transfer attributes for the continuous SCK mode are set according to the following rules When the DSPI is in SPI configuration CTAR0 i...

Page 989: ...led Figure 20 41 Continuous SCK Timing Diagram CONT 0 If the CONT bit in the TX FIFO entry is set or the DCONT in the DSPIx_DSICR is set PCS remains asserted between the transfers when the PCS signal...

Page 990: ...us Register DSPIx_SR See Figure 20 34 and Figure 20 35 that illustrate when EOQF is set 20 4 9 2 Transmit FIFO Fill Interrupt or DMA Request TFFF The transmit FIFO fill request indicates that the TX F...

Page 991: ...the state of the ROOE bit in the DSPIx_MCR the data from the transfer that generated the overflow is either ignored or shifted in to the shift register If the ROOE bit is set the incoming data is shif...

Page 992: ...the DSPIx_SR is set If EOQF flag is set to 1 the serial interface is disabled preventing data transmission and reception The DSPI is put into the STOPPED state and the TXRXS bit is negated to indicate...

Page 993: ...te Scaler Values DSPI_CTAR BR 2 25 0 MHz 16 7 MHz 10 0 MHz 7 14 MHz 4 12 5 MHz 8 33 MHz 5 00 MHz 3 57 MHz 6 8 33 MHz 5 56 MHz 3 33 MHz 2 38 MHz 8 6 25 MHz 4 17 MHz 2 50 MHz 1 79 MHz 16 3 12 MHz 2 08 M...

Page 994: ...s to match the default cases for the possible combinations of the MPC5xx family control bits in its command RAM The defaults for the MPC5xx family are based on a system clock of 40 MHz Table 20 32 Del...

Page 995: ...mapped pointer and a memory mapped counter for each FIFO The pointer to the first in entry in each FIFO is memory mapped For the TX FIFO the first in pointer is the transmit next pointer TXNXTPTR For...

Page 996: ...base base address of transmit FIFO TXCTR transmit FIFO counter TXNXTPTR transmit next pointer TX FIFO depth transmit FIFO depth implementation specific 20 5 5 2 Address Calculation for the First in E...

Page 997: ...Deserial Serial Peripheral Interface DSPI MPC5566 Microcontroller Reference Manual Rev 2 20 72 Freescale Semiconductor...

Page 998: ...eSCI Block Diagram IRQ generation Receive wake up control Receive shift register eSCI data register LIN receive register LIN transmit register DMA interface TX DMA RX DMA RDRF OR IRQ ORING IRQ to CPU...

Page 999: ...I registers via the slave bus When the eSCI module is not used in the application set the MDIS bit 21 1 3 Features The eSCI includes these features Full duplex operation Standard mark space non return...

Page 1000: ...2 eSCI Receive Pin RXDA RXDB These signals receive data input for the eSCI 21 3 Memory Map and Register Definition 21 3 1 Overview This section provides a detailed description of all memory and regist...

Page 1001: ...ol register 1 32 Base 0x0004 ESCIx_CR2 eSCI control register 2 16 Base 0x0006 ESCIx_DR eSCI data register 16 Base 0x0008 ESCIx_SR eSCI status register 32 Base 0x000C ESCIx_LCR LIN control register 32...

Page 1002: ...tart bit 8 data bits 1 stop bit 1 1 start bit 9 data bits 1 stop bit 20 WAKE Wake up condition Determines which condition wakes up the eSCI a logic 1 address mark in the most significant bit MSB posit...

Page 1003: ...le Enables the receive data register full flag ESCIx_SR RDRF and the overrun flag ESCIx_SR OR to generate interrupt requests The interrupt is suppressed in RX DMA mode 0 RDRF and OR interrupt requests...

Page 1004: ...Field Description 0 MDIS Module disable By default the module is enabled but can be disabled by writing a 1 to this bit DMA requests are negated if the device is in module disable mode 0 Module enable...

Page 1005: ...SCI when a bit error is asserted This allows to stop driving the LIN bus quickly after a bit error has been detected 0 Byte is completely transmitted 1 Byte is partially transmitted 10 11 Reserved 12...

Page 1006: ...8 R8 is the ninth data bit received when the eSCI is configured for 9 bit data format M 1 1 T8 Transmit bit 8 T8 is the ninth data bit transmitted when the eSCI is configured for 9 bit data format M 1...

Page 1007: ...a register since last time software cleared RDRF 1 Received data available in eSCI data register 3 IDLE Idle line flag IDLE is set when 10 consecutive logic 1s if M 0 or 11 consecutive logic 1s if M 1...

Page 1008: ...set when the ESCIx_LTR register becomes free Write a one to TXRDY to clear it to 0 18 LWAKE Received LIN wake up signal A LIN slave has sent a wake up signal on the bus When this signal is detected t...

Page 1009: ...wake up signal on the LIN bus This must be set before a transmission if the bus is in sleep mode This bit auto clears so a read from this bit always returns 0 According to LIN 2 0 generating a valid...

Page 1010: ...REG ready interrupt enable Generates an Interrupt when new data can be written to the LIN TXREG For a list of interrupt enables and flags Refer to Table 21 21 10 WUIE RX wake up interrupt enable Gener...

Page 1011: ...L0 T8 T0 D0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21 7 LIN Transmit Reg...

Page 1012: ...RC pattern as required LIN 1 x slaves only accepts frames with 2 4 or 8 data bytes 8 31 Reserved Table 21 10 ESCIx_LTR Third Byte Field Descriptions Field Description 0 HDCHK Header checksum enable In...

Page 1013: ...e is specified in multiples of bit times The timeout period starts with the transmission of the LIN break character 8 31 Reserved Table 21 11 ESCIx_LTR Rx Frame Fourth Byte Field Description Field Des...

Page 1014: ...nformation are not available in the ESCIx_LRR unless they are treated as data It is possible to treat CRC and checksum bytes as data by deactivating the CSUM respectively CRC control bits in the ESCIx...

Page 1015: ...gh they use the same baud rate generator The CPU monitors the status of the eSCI writes the data to be transmitted and processes received data Figure 21 11 eSCI Operation Block Diagram Table 21 14 ESC...

Page 1016: ...s has a total of 11 bits The two different data formats are illustrated in Figure 21 12 Table 21 15 and Table 21 16 show the number of each type of bit in 8 bit data format and 9 bit data format respe...

Page 1017: ...rate of 16 samples per bit time Baud rate generation is subject to one source of error when integer division of the system clock does not result in the exact target frequency Table 21 17 lists some e...

Page 1018: ...register then shifts a frame out through the TXD signal after it has prefaced them with a start bit and appended them with a stop bit The eSCI data register ESCIx_DR is the buffer write only during tr...

Page 1019: ...d to ESCIx_DR where the ninth bit is written to the T8 bit in ESCIx_DR if the eSCI is in 9 bit data format 3 Repeat step 2 for each subsequent transmission NOTE The TDRE flag is set when the shift reg...

Page 1020: ...haracter length depends on the M bit in the eSCI control register 1 ESCIx_CR1 and on the BRK13 bit in the eSCI control register 2 ESCIx_CR2 As long as SBK is set the transmitter logic continuously loa...

Page 1021: ...er than flagging them after a byte transmission has completed To use this feature it is assumed a physical interface connects to the LIN bus as shown in Figure 21 14 Figure 21 14 Fast Bit Error Detect...

Page 1022: ...1 ESCIx_CR1 determines the bit length of data characters When receiving 9 bit data bit R8 in the eSCI data register ESCIx_DR is the ninth bit bit 8 Clock BESM13 0 BESM13 1 1 3 5 7 9 11 13 15 2 4 6 8...

Page 1023: ...is re synchronized refer to Figure 21 17 After every start bit After the receiver detects a data bit change from logic 1 to logic 0 This data bit change is detected when a majority of data samples ret...

Page 1024: ...9 and RT10 start bit samples are logic 1s following a successful start bit verification the noise flag NF is set To verify a stop bit and to detect noise recovery logic takes samples at RT8 RT9 and RT...

Page 1025: ...nsmitting device operates at a baud rate below or above the receiver baud rate accumulated bit time misalignment can cause one of the three stop bit data samples RT8 RT9 and RT10 to fall outside the s...

Page 1026: ...x 16 RT cycles 147 RT cycles The maximum percent difference between the receiver count and the transmitter count of a slow 8 bit data character with no errors is 4 63 as is shown below For a 9 bit da...

Page 1027: ...cles as shown below With the misaligned character shown in Figure 21 20 the receiver counts 170 RT cycles at the point when the count of the transmitting device is 11 bit times x 16 RT cycles 176 RT c...

Page 1028: ...racter that wakes a receiver does not set the receiver idle bit ESCIx_SR IDLE or the receive data register full flag RDRF The idle line type bit ESCIx_CR1 ILT determines whether the receiver begins co...

Page 1029: ...led Refer to Section 6 3 1 12 Pad Configuration Registers SIU_PCR During transmission the transmitter must be enabled TE 1 the receiver can be enabled or disabled If the receiver is enabled RE 1 trans...

Page 1030: ...it data register ESCIx_DR is empty and that a new data can be written to the ESCIx_DR for transmission The TDRE bit is cleared by writing a one to the TDRE bit location in the ESCIx_SR ESCIx_SR 0 TIE...

Page 1031: ...the receiver ready RXRDY flag is set when the eSCI receives a valid data byte in an RX frame RXRDY is not set for bytes which the receiver obtains by reading back the data which the LIN finite state...

Page 1032: ...bit generation are also available for use in LIN mode LIN CKERR Checksum error detected If an RX frame has the checksum checking flag set and the last byte does not match the calculated checksum the...

Page 1033: ...y large frames The eSCI and FlexCAN modules use the same CRC polynomial the LIN protocol processes CAN bytes as data bytes Figure 21 24 LIN Frame with CRC bytes To force a resync of the LIN FSM use th...

Page 1034: ...10 3 Generating an RX Frame For RX frames the header information is provided by the LIN master The data CRC and checksum bytes as enabled are provided by the LIN slave The LIN master verifies CRC and...

Page 1035: ...ter the LIN FSM returns to its start state and the STO interrupt is issued The LIN protocol supports a sleep mode After 25 000 bus cycles of inactivity the bus is assumed to be in sleep mode Normally...

Page 1036: ...ect 8 data bits and disable the parity bit PE 0 4 Use the LIN interrupts by clearing the interrupt enable bits ESCIx_CR1 TIE ESCIx_CR1 TCIE and ESCIx_CR1 RIE Select LIN mode by setting ESCIx_LCR LIN 1...

Page 1037: ...Enhanced Serial Communication Interface eSCI MPC5566 Microcontroller Reference Manual Rev 2 21 40 Freescale Semiconductor...

Page 1038: ...N protocol according to CAN Specification version 2 0B and ISO Standard 11898 Each FlexCAN2 module contains a 1024 byte embedded memory capable of storing up to 64 message buffers MBs The respective f...

Page 1039: ...the specific requirements of this field real time processing reliable operation in the EMI environment of a vehicle cost effectiveness and required bandwidth The FlexCAN2 module is a full implementati...

Page 1040: ...revious versions or individual receive ID masking Maskable self reception by setting MCR SRXDIS Full implementation of the CAN protocol specification version 2 0B Standard data and remote frames Exten...

Page 1041: ...es in a CAN error passive mode freezing all error counters and receiving messages without sending acknowledgments 22 1 4 4 Loop Back Mode The module enters this mode when the LPB bit in the CANx_CR is...

Page 1042: ...evel 1 22 2 2 2 CNTXx This pin is the transmit pin to the CAN bus transceiver The dominant state is represented by logic level 0 The recessive state is represented by logic level 1 22 3 Memory Map Reg...

Page 1043: ...onfiguration register 32 Base 0x0004 CANx_CR Control register 32 Base 0x0008 CANx_TIMER Free running timer 32 Base 0x000C Reserved Base 0x0010 CANx_RXGMASK RX global mask 32 Base 0x0014 CANx_RX14MASK...

Page 1044: ...0x000C Data byte 4 Data byte 5 Data byte 6 Data byte 7 Figure 22 2 Message Buffer Structure Table 22 4 Message Buffer Field Descriptions Name Description CODE Message buffer code This 4 bit field can...

Page 1045: ...for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus ID Frame identifier Standard frame format the 11 3 13 most significant bits MSB are the frame ID in...

Page 1046: ...Transmission Description X 1000 INACTIVE MB does not participate in the arbitration process 0 1100 1000 Transmit data frame unconditionally once After transmission the MB automatically returns to the...

Page 1047: ...6 2 Module Disabled Mode for more information 0 Enable the FlexCAN2 module 1 Disable the FlexCAN2 module 1 FRZ Freeze enable Specifies the FlexCAN2 behavior when the HALT bit in the CANx_MCR is set or...

Page 1048: ...and reception processes have finished Therefore the software can poll the FRZACK bit to know when FlexCAN2 has actually entered freeze mode If freeze mode request is negated then this bit is negated a...

Page 1049: ...eception queue i e a received message always fills the first matching buffer setting the CODE field to overrun if the buffer contained an unread message See Section 22 3 3 4 RX Mask Registers for more...

Page 1050: ...4 5 4 Protocol Timing 8 9 RJW 0 1 Resync jump width Defines the maximum number of time quanta1 that a bit time can be changed by one re synchronization The valid programmable values are 0 3 10 12 PSEG...

Page 1051: ...is asserted automatic recovering from bus off is disabled and the module remains in bus off state until the bit is negated by the user If the negation occurs before 128 sequences of 11 recessive bits...

Page 1052: ...e to the register Software can poll the register to verify the data is written 22 3 3 4 RX Mask Registers By negating the CANx_MCR MBFEN bit the CANx_RXGMASK CANx_RX14MASK and CANx_RX15MASK registers...

Page 1053: ...ended ID ID17 ID0 Match MB2 ID 1 1 1 1 1 1 1 1 0 0 0 0 MB3 ID 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MB4 ID 0 0 0 0 0 0 1 1 1 1 1 0 MB5 ID 0 0 0 0 0 0 1 1 1 0 1 1 0 1 0 1 0 1 0 1...

Page 1054: ...ANx_RXIMR 0 63 registers are used as acceptance masks for received frame IDs in both standard and extended ID formats One mask register is provided for each message buffer for individual ID masking pe...

Page 1055: ...xCAN2 module Both counters are read only except in freeze mode where they can be written by the CPU Writing to the CANx_ECR while in freeze mode is an indirect operation The data is first written to a...

Page 1056: ...tance of dominant bit following a stream of less than 11 consecutive recessive bits the internal counter resets itself to zero without affecting the TXECTR value If during system start up only one nod...

Page 1057: ...reached 96 If the corresponding mask bit in the Control Register TWRNMSK is set an interrupt is generated to the CPU This bit is cleared by writing to 1 Writing 0 has no effect 0 No such occurrence 1...

Page 1058: ...ge transmission 0 No such occurrence 1 TXECTR 96 23 RXWRN RX error counter This status bit indicates when repetitive errors are occurring during messages reception 0 No such occurrence 1 RXECTR 96 24...

Page 1059: ...ated to the CPU This bit is cleared by writing it to 1 Writing 0 has no effect 0 No such occurrence 1 Indicates setting of any error bit in the CANx_ESR 31 Reserved Address Base 0x0024 Access User R W...

Page 1060: ...0 0 0 0 0 0 0 0 0 0 0 Figure 22 11 Interrupt Masks Low Register CANx_IMRL Table 22 14 CANx_IMRL Field Descriptions Field Description 0 31 BUFnM Message buffer n mask Enables or disables the respective...

Page 1061: ...t represents the respective FlexCAN2 message buffer MB63 MB32 interrupt Write 1 to clear 0 No such occurrence 1 The corresponding buffer has successfully completed transmission or reception Address Ba...

Page 1062: ...ner MB defined in a previous arbitration was deactivated or if there was no MB to transmit but the CPU wrote to the C S word of any MB after the previous arbitration finished When MBM is in idle or bu...

Page 1063: ...ay Control and status word mandatory activates internal lock for this buffer ID optional needed only if a mask was used DATA field words Free running timer optional releases internal lock Reading the...

Page 1064: ...be programmed if the MBFEN bit is asserted while the module is in freeze mode FlexCAN also supports an alternate masking scheme with only three mask registers CANx_RXGMASK CANx_RX14MASK and CANx_RX15...

Page 1065: ...n FlexCAN2 can transmit a MB with an ID that is not the lowest at that time 22 4 4 2 Notes on RX Message Buffer Deactivation If the deactivation occurs during move in the move operation is aborted and...

Page 1066: ...remote frame by writing the MB as transmit with the RTR bit set to 1 After the remote request frame is transmitted successfully the MB becomes a receive message buffer with the same ID as before When...

Page 1067: ...V PROPSEG PSEG1 PSEG2 and RJW See Section 22 3 3 2 Control Register CANx_CR The PRESDIV field controls a prescaler that generates the serial clock SCK whose period defines the time quantum used to com...

Page 1068: ...us during this period Transmit point A node in transmit mode transfers a new value to the CAN bus at this point Sample point A node in receive mode samples the bus at this point If the three samples p...

Page 1069: ...the HALT bit in the CANx_MCR or when the MCU is put into debug mode In both cases it is also necessary that the FRZ bit is asserted in the CANx_MCR When freeze mode is requested during transmission or...

Page 1070: ...s the CANx_MCR MDISACK bit 22 4 7 Interrupts The module can generate interrupts from 20 interrupt sources 16 interrupts due to message buffers one interrupt due to an error condition two interrupts fo...

Page 1071: ...level soft reset A soft reset is synchronous and must follow an internal request acknowledge procedure across clock domains Therefore it can take some time to fully propagate its effects The SOFTRST...

Page 1072: ...rted initialize CANx_RXIMR 0 63 for individual acceptance masking 4 Set required mask bits in CANx_IMRH and CANx_IMRL registers for all MBs interrupts and in CANx_CR for bus off and error interrupts 5...

Page 1073: ...MPC5566 Microcontroller Reference Manual Rev 2 22 36 Freescale Semiconductor...

Page 1074: ...contains POR circuits for the 1 5 V supply VDDSYN and the VDDE supply that powers the RESET pad 23 1 1 Block Diagram The block diagram of the VRC and POR module is shown in Figure 23 1 The diagram re...

Page 1075: ...stor while the 3 3 V POR is asserted The pass transistor is completely turned on by the time the 3 3 V POR negates Table 23 1 Voltage Regulator Controller and POR Block External Signals Signal Type Si...

Page 1076: ...being monitored drops below the specified threshold The entire device is in power on reset if any of these supplies are below the values specified in the MPC5566 Microcontroller Data Sheet Power on re...

Page 1077: ...ircuit The 3 3 V POR circuit is used to ensure that VDDSYN is high enough that the FMPLL begins to operate correctly 23 4 2 3 RESET Power POR Circuit The RESET power POR circuit monitors the supply th...

Page 1078: ...owing power sequencing requirements for the device If an external 1 5 V power supply is used and VRC33 is tied to ground power sequencing is required between the 1 5 V power supply and VDDSYN and the...

Page 1079: ...RC33 Grounded The 1 5 V VDD supply must rise to 1 35 V before the 3 3 V VDDSYN and the RESET supplies rise above 2 0 V This ensures that digital logic in the PLL for the 1 5 V supply does not begin to...

Page 1080: ...Refer to the following sections or documents for more information Section 23 5 3 4 Pin Values after POR Negates MPC5566 Microcontroller Data Sheet for the VDD33_LAG specification 23 5 3 4 Pin Values...

Page 1081: ...Voltage Regulator Controller VRC and POR Module MPC5566 Microcontroller Reference Manual Rev 2 23 8 Freescale Semiconductor...

Page 1082: ...de select TMS and test clock input TCK TDI TDO TMS and TCK are compliant with the IEEE 1149 1 2001 standard and are shared with the NDI through the test access port TAP interface 24 1 1 Block Diagram...

Page 1083: ...gister a boundary scan register and a device identification register The size of the boundary scan register is 480 bits A TAP controller state machine that controls the operation of the data registers...

Page 1084: ...s Mode When no test operation is required the BYPASS instruction can be loaded to place the JTAGC into bypass mode While in bypass mode the single bit bypass shift register is used to provide a minimu...

Page 1085: ...he TAP controller is in the Shift IR state and latched on the falling edge of TCK in the Update IR state The latched instruction value can only be changed in the update IR and test logic reset TAP con...

Page 1086: ...when the EXTEST SAMPLE or SAMPLE PRELOAD instructions are active It is used to capture input pin data force fixed values on output pins and select a logic value and direction for bidirectional pins E...

Page 1087: ...struction For more detail on TAP sharing via JTAGC instructions refer to Section 24 4 4 2 ACCESS_AUX_TAP_x Instructions Data is shifted between TDI and TDO though the selected register starting with t...

Page 1088: ...achine Test logic reset Run test idle Select DR scan Select IR scan Capture DR Capture IR Shift DR Shift IR Exit1 DR Exit1 IR Pause DR Pause IR Exit2 DR Exit2 IR Update DR Update IR 1 0 1 1 1 0 0 0 0...

Page 1089: ...ctions This section gives an overview of each instruction refer to the IEEE 1149 1 2001 standard for more details The JTAGC implements the IEEE 1149 1 2001 defined instructions listed in Table 24 3 Ta...

Page 1090: ...uction CLAMP allows the state of signals driven from MCU pins to be determined from the boundary scan register while the bypass register is selected as the serial path between TDI and TDO CLAMP enhanc...

Page 1091: ...e instruction samples the system data and control signals on the MCU input pins and just before the boundary scan register cells at the output pins This sampling occurs on the rising edge of TCK in th...

Page 1092: ...ow state without loss of data However the system clock is not synchronized to TCK internally Any mixed operation using both the test logic and the system functional logic requires external synchroniza...

Page 1093: ...IEEE 1149 1 Test Access Port Controller JTAGC MPC5566 Microcontroller Reference Manual Rev 2 24 12 Freescale Semiconductor...

Page 1094: ...rface NZ6C3 In this chapter the NZ6C3 interface is discussed in Section 25 10 e200z6 Class 3 Nexus Module NZ6C3 through Section 25 11 NZ6C3 Memory Map and Register Definition Nexus crossbar eDMA inter...

Page 1095: ...ced port mode RPM FPM comprises 12 MDO pins and RPM comprises 4 MDO pins Auxiliary output port One MCKO message clock out pin Four or 12 MDO message data out pins JCOMP Program data ownership watchpoi...

Page 1096: ...uction fetches via private opcodes Subset of Power Architecture Book E software debug facilities with OnCE block Nexus class 1 features eDMA development support features NXDM Data trace via data write...

Page 1097: ...gnal negation of JCOMP or through state machine transitions controlled by TMS Assertion of JCOMP allows the NDI to move out of the reset state and is a prerequisite to grant Nexus clients control of t...

Page 1098: ...s modules in reset as well This prevents Nexus read write to memory mapped resources and the transmission of Nexus trace messages Refer to Table 13 17 for information on Nexus port enabling and disabl...

Page 1099: ...bus used is determined by the Nexus PCR FPM configuration Following a power on reset MDO 0 remains asserted until power on reset is exited and the system clock achieves lock 25 2 1 4 Message Start End...

Page 1100: ...Table 25 2 shows the NDI registers by Client Source ID and Index values Table 25 2 Nexus Development Interface NDI Registers Client Source ID Index Register e200z6 Control and Status Registers1 0b000...

Page 1101: ...AHB_DTSA2n 0b0101 18 eDMA 2 Data Trace End Address 0 AHB_DTEA1n 0b0101 19 eDMA 2 Data Trace End Address 1 AHB_DTEA2n 0b0101 22 eDMA 2 Breakpoint Watchpoint Control 1 AHB_BWC1n 0b0101 23 eDMA 2 Breakpo...

Page 1102: ...er PCR eTPU CDC Control Status Registers 0b0100 13 eTPU CDC Data Trace Control NDEDI_CDC_DTC eTPU1 eTPU2 CDC Shared Control Status Registers 0b0010 or 0b0011 or 0b0100 65 eTPU Data Trace Address Range...

Page 1103: ...ions supported by Nexus clients can be found in the relevant sections of this chapter 001 0011 001 1111 Reserved 010 0000 Instruction Address Compare 1 IAC1 010 0001 Instruction Address Compare 2 IAC2...

Page 1104: ...0 Enables access to the NPC TAP controller ACCESS_AUX_TAP_ONCE 10001 Enables access to the e200z6 OnCE TAP controller ACCESS_AUX_TAP_eTPU 10010 Enables access to the eTPU Nexus TAP controller ACCESS_A...

Page 1105: ...identify which source generated the message Table 25 8 shows the values used for the SRC field by the different clients on the device These 4 bit values are specific to the device The same values are...

Page 1106: ...orts while appearing to the development tool as a single module 25 5 2 Features The NPC performs the following functions Controls arbitration for ownership of the Nexus auxiliary output port Nexus dev...

Page 1107: ...ed instructions Instructions are shifted in through TDI while the TAP controller is in the Shift IR state and latched on the falling edge of TCK in the Update IR state The latched instruction value ca...

Page 1108: ...umber Design Center Part Identification Number W Reset 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Part Identification Number continued Manufacturer Identity Code 1 W Reset...

Page 1109: ...d or disabled by the FPM setting 30 MCKO_GT MCKO clock gating control Enables or disables MCKO clock gating If clock gating is enabled the MCKO clock is gated when the NPC is in enabled mode but not a...

Page 1110: ...External Signal Description 25 7 2 1 Output Message Protocol The protocol for transmitting messages via the auxiliary port is accomplished with the MSEO functions The MSEO pins are used to signal the...

Page 1111: ...MDO pins The device ID message can also be sent out serially through TDO Table 25 13 describes the device ID message that the NPC can transmit on the auxiliary port The TCODE is the first packet trans...

Page 1112: ...length packets may start and or end on a single clock When any packet follows a variable length packet it must start on a port boundary The field containing the TCODE number is always transferred out...

Page 1113: ...shifted between TDI and TDO starting with the least significant bit as illustrated in Figure 25 8 This applies for the instruction register and all Nexus tool mapped registers Figure 25 8 Shifting Dat...

Page 1114: ...RUN TEST IDLE SELECT DR SCAN SELECT IR SCAN CAPTURE DR CAPTURE IR SHIFT DR SHIFT IR EXIT1 DR EXIT1 IR PAUSE DR PAUSE IR EXIT2 DR EXIT2 IR UPDATE DR UPDATE IR 1 0 1 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0...

Page 1115: ...in the UPDATE IR state At this point the Nexus controller state machine shown in Figure 25 10 transitions to the REG_SELECT state The Nexus controller has three states idle register select and data ac...

Page 1116: ...the value is loaded from the IEEE 1149 1 2001 shifter to the register during the UPDATE DR state When reading a register there is no requirement to shift out the entire register contents Shifting may...

Page 1117: ...MCKO is an output clock to the development tools used for the timing of MSEO and MDO pin functions MCKO is derived from the system clock and its frequency is determined by the value of the MCKO_DIV 2...

Page 1118: ...instruction in the JTAGC 2 Load the TAP controller with the NEXUS ENABLE instruction To write control data to NPC tool mapped registers the following sequence is required 1 Write the 7 bit register i...

Page 1119: ...rite access via the JTAG interface Reg Index 0 Access R O 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R PRN DC PIN W Reset 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R P...

Page 1120: ...omitted and the configuration in this chapter describes an NPC with a dedicated auxiliary port The auxiliary port is fully described in Section 25 2 External Signal Description 25 10 2 Block Diagram F...

Page 1121: ...sage DRM External visibility of data reads to memory mapped resources Data Write Message DWM External visibility of data writes to memory mapped resources Data Trace Messaging DTM External visibility...

Page 1122: ...write ready pin nex_rdy_b pin One watchpoint event pin nex_evto_b One event in pin nex_evti_b One MCKO message clock out pin Registers for program trace data trace ownership trace and watchpoint trigg...

Page 1123: ...d Debug status register DS 31 24 Ownership Trace Message 6 6 TCODE Fixed TCODE number 2 0x02 4 4 SRC Fixed Source processor identifier 32 32 PROCESS Fixed Task Process ID tag Program Trace Direct Bran...

Page 1124: ...Message w Sync1 6 6 TCODE Fixed TCODE number 12 0x0C 4 4 SRC Fixed Source processor identifier 1 8 I CNT Variable Number of sequential instructions executed since last taken branch 1 32 F ADDR Variab...

Page 1125: ...w 4 4 SRC Fixed Source processor identifier 1 8 I CNT Variable Number of sequential instructions executed since last taken branch 1 32 U ADDR Variable Unique part of target address for taken branches...

Page 1126: ...am trace The advantages for each are discussed in Section 25 13 1 Branch Trace Messaging BTM If the branch history method is selected the shaded TCODES above are not messaged out Table 25 20 Error Cod...

Page 1127: ...Branch History This type of packet is terminated by a stop bit set to a 1 after the last history bit Table 25 22 Event Code Encoding TCODE 33 Event Code Description 0000 Entry into Debug Mode 0001 En...

Page 1128: ...the register map for the NZ6C3 module Table 25 24 NZ6C3 Memory Map Access Opcode Register Name Register Description Read Address Write Address 0x0001 CSC Client select control 1 1 The CSC and PCR regi...

Page 1129: ...MCK_DIV 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Nexus Reg PCR_INDEX R W Reset 0x0 Table 25 25 Port Configuration Register Fields PCR 31 OPC OPC Output...

Page 1130: ...31 OPC1 Output port mode control 0 Reduced port mode configuration four MDO pins 1 Full port mode configuration 12 MDO pins 30 29 MCK_DIV 1 0 1 MCKO clock divide ratio refer to note below 00 MCKO is...

Page 1131: ...R but have no effect Nexus Reg 0x0003 Access R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R EWC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0...

Page 1132: ...5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DBG 0 0 0 LPC CHK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 25 17 Developm...

Page 1133: ...set 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CNT ERR DV W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 25 18 Read Write Access Control and Status Register RWCS Table 25...

Page 1134: ...ess Status Bit Encoding Read Action Write Action ERR DV Read access has not completed Write access completed without error 0 0 Read access error has occurred Write access error has occurred 1 0 Read a...

Page 1135: ...Program trace start control 000 Trigger disabled 001 Use watchpoint 0 IAC1 from Nexus1 010 Use watchpoint 1 IAC2 from Nexus1 011 Use watchpoint 2 IAC3 from Nexus1 100 Use watchpoint 3 IAC4 from Nexus...

Page 1136: ...watchpoint 0 IAC1 from Nexus1 010 Use watchpoint 1 IAC2 from Nexus1 011 Use watchpoint 2 IAC3 from Nexus1 100 Use watchpoint 3 IAC4 from Nexus1 101 Use watchpoint 4 DAC1 from Nexus1 110 Use watchpoin...

Page 1137: ...trace 2 0 Condition trace on data accesses 1 Condition trace on instruction accesses 1 0 Reserved Nexus Reg 0x000E Access R W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6...

Page 1138: ...tions with all Nexus3 registers according to the register map in Table 25 24 Reading writing of a NZ6C3 register then requires two 2 passes through the data scan DR path of the JTAG state machine refe...

Page 1139: ...e information is messaged via the auxiliary port using an ownership trace message OTM The e200z6 processor contains a Power Architecture Book E defined process ID register within the CPU The process I...

Page 1140: ...gure 25 28 Error Message Format 25 12 3 OTM Flow Ownership trace messages are generated when the operating system writes to the e200z6 process ID register or the memory mapped ownership trace register...

Page 1141: ...of the indirect branch address Number of sequential instructions executed since the last exception was processed as well as the unique portion of the exception vector address Number of sequential inst...

Page 1142: ...ed as consecutive bits in the history field Branch history messages solve predicated instruction tracking and save bandwidth since only indirect branches cause messages to be queued 25 13 1 4 BTM Usin...

Page 1143: ...format Figure 25 29 Indirect Branch Message History Format 25 13 2 2 Indirect Branch Messages Traditional If DC PTM is cleared indirect branch information is messaged out in the following format Figur...

Page 1144: ...art of the resource full message This information can be concatenated by the tool with the branch predicate history information from subsequent messages to obtain the complete branch history for a mes...

Page 1145: ...is empty an error message is queued The error encoding indicates which message types were denied queueing while the FIFO was emptying If only a program trace message attempts to enter the queue while...

Page 1146: ...Upon direct indirect branch after the sequential instruction counter has expired indicating 255 instructions have occurred between branches Upon direct indirect branch after a BTM message was lost due...

Page 1147: ...e periodic program trace message counter then resets Event In If the Nexus module is enabled an EVTI assertion initiates a direct indirect branch with sync message upon the next direct indirect branch...

Page 1148: ...of the most significant 0 padded message address with the previously decoded address gives the current address Previous address A1 0x0003FC01 New address A2 0x0003F365 Figure 25 38 Relative Address Ge...

Page 1149: ...y messages I CNT represents the number of instructions executed since the last taken non taken direct branch last taken indirect branch or exception Not taken indirect branches are considered sequenti...

Page 1150: ...DRM as per the IEEE ISTO 5001 2003 standard TCODE 28 MCKO MSEO Source Processor 0b0000 Number of Sequential Instructions 0 Relative Address 0xA5 Branch History 0b1010_0101 with Stop MDO 1 0 11 01 00...

Page 1151: ...tchpoints are configured within the Nexus1 module 25 14 6 2 DTM Message Formats The Nexus3 module supports five types of DTM messages data write data read data write synchronization data read synchron...

Page 1152: ...01000 NOTE The OVC bits within the DC1 register can be set to delay the CPU to alleviate but not eliminate potential overrun situations Error information is messaged out in the following format Figure...

Page 1153: ...ge is converted to a data write read with sync message Queue Overrun An error message occurs when a new message cannot be queued due to a full message queue The FIFO discards messages until it has com...

Page 1154: ...the address range defined by the DTEA and DTSA registers and by the RC1 2 field in the DTC All e200z6 initiated read write accesses which fall inside or outside these address ranges as programmed are...

Page 1155: ...ool must use this indication to invalidate the previous DTM 25 14 6 4 Data Trace Timing Diagrams Eight MDO Configuration Figure 25 47 Data Trace Data Write Message e200z6 bus cycle accesses misaligned...

Page 1156: ...is supported through the e200z6 Nexus1 module The e200z6 Nexus1 module is capable of setting multiple address and or data watchpoints Please refer to the e200z6 Core Reference Manual for more informat...

Page 1157: ...hpoint only error encoding 00110 If an OTM and or program trace and or data trace message also attempts to enter the queue while it is being emptied the error message incorporates error encoding 01000...

Page 1158: ...ther non cached memory can be accessed via the standard memory map settings All accesses are setup and initiated by the read write access control status register RWCS as well as the read write access...

Page 1159: ...xus register index of 0xA refer to Table 25 24 Configure as follows Write Data 0xnnnnnnnn write data 4 The NZ6C3 module then arbitrates for the system bus and transfer the data value from the data buf...

Page 1160: ...r each access within the burst the address from the RWA register is incremented to the next doubleword size specified in the SZ field modulo the length of the burst and the number from the CNT field i...

Page 1161: ...fer has completed without error ERR 0b0 the address from the RWA register is incremented to the next word size specified in the SZ field and the number from the CNT field is decremented Nexus then ass...

Page 1162: ...ccurs 1 The access is terminated without re trying AC bit is cleared 2 The ERR bit in the RWCS register is set 3 The error message is sent TCODE 8 indicating read write error 25 14 8 7 2 Access Termin...

Page 1163: ...ress variable Table 25 41 illustrates an example of direct branch message with 12 MDO and 2 MSEO Note that T0 and I0 are the least significant bits where Tx TCODE number fixed Sx Source processor fixe...

Page 1164: ...r end of last message 1 I1 I0 S3 S2 S1 S0 T5 T4 T3 T2 T1 T0 0 0 Start Message 2 0 0 0 0 0 0 0 0 0 0 I3 I2 1 1 End Packet and End Message 3 X X X X S1 S0 T5 T4 T3 T2 T1 T0 0 0 Start of Next Message Tab...

Page 1165: ...and write to read write access address register RWA 2 37 Write RWA initialize starting read address data input on TDI 3 13 Nexus Command write to read write control status register RWCS 4 37 Write RWC...

Page 1166: ...ences are made to the auxiliary port and its specific signals such as MCKO MSEO 1 0 MDO 12 0 and others In actual use the device NPC module arbitrates the access of the single auxiliary port To simpli...

Page 1167: ...25 16 External Signal Description The NXDM module uses the same pins and pin protocol as defined in Section 25 2 External Signal Description 25 16 1 Rules for Output Messages The NXDM module observe...

Page 1168: ...shown for reference only 0x1 R 0x02 Port Configuration Register PCR 1 Refer to NPC R W Development Control 1 DC1_n 0x2 R W 0x04 0x05 Development Control 2 DC2_n 0x3 R W 0x05 0x06 Watchpoint Trigger WT...

Page 1169: ...functions are controlled globally by the NPC port control register PCR Output port mode control 0 Reduced port mode configuration 1 Full port mode configuration 30 29 MCK_DIV1 MCK_DIV nexus message c...

Page 1170: ...25 56 Development Control Register 2 DC2 Table 25 48 DC2 Field Description Field Description 31 24 EWC1 1 The EOC bits in DC1 must be programmed to trigger EVTO on watchpoint occurrence for the EWC b...

Page 1171: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 DTS DTE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1172: ...ated X1 Enable data read trace 1X Enable data write trace 27 8 Reserved read as 0 7 RC1 Range control 1 0 Condition trace on address within range endpoints inclusive 1 Condition trace on address outsi...

Page 1173: ...17 2 6 Breakpoint Watchpoint Control Register 1 BWC1 Breakpoint watchpoint control register 1 controls attributes for generation of NXDM watchpoint number 1 Access R W 31 30 29 28 27 26 25 24 23 22 2...

Page 1174: ...oint 1 register compare 00 No register compare same as BWC1 31 30 2 b00 01 Reserved 10 Compare with BWA1 value 11 Reserved 15 BWT1 Breakpoint watchpoint 1 type 0 Reserved 1 Watchpoint 1 on data access...

Page 1175: ...ool 25 17 2 11 IEEE 1149 1 JTAG Test Access Port The NXDM module uses the IEEE 1149 1 TAP controller for accessing Nexus resources The JTAG signals themselves are shared by all TAP controllers on the...

Page 1176: ...ccess via JTAG Access to Nexus register resources is enabled by loading a single instruction NEXUS_ACCESS into the JTAG Instruction Register IR This IR is part of the IEEE 1149 1 TAP controller within...

Page 1177: ...te 25 17 3 Functional Description 25 17 4 Enabling NXDM Operation The NXDM module is enabled by loading a single instruction ACCESS_AUX_TAP_DMA as shown in Table 25 4 into the JTAG instruction registe...

Page 1178: ...rce processor identifier multiple Nexus configuration 3 3 DSZ Fixed Data size refer to Table 25 58 1 32 U ADDR Variable Unique portion of the data read value 1 64 DATA Variable Data read value Error M...

Page 1179: ...Data Trace overrun 00011 Reserved 00100 Reserved 00101 Invalid access opcode Nexus Register unimplemented 00110 Watchpoint overrun 00111 Reserved 01000 Data Trace and Watchpoint overrun 01001 11111 R...

Page 1180: ...ata read messages contain the data write read value and the address of the write read access relative to the previous data trace message Data write message and data read message information is message...

Page 1181: ...message occurred Upon assertion of the Event In EVTI pin the first data trace message is a synchronization message if the eic bits of the dc register have enabled this feature Upon data trace write re...

Page 1182: ...ued due to the message queue being full The FIFO discards messages until it has completely emptied the queue After it is emptied an error message is queued The error encoding indicates the types of me...

Page 1183: ...ach DTM channel Data trace windowing is achieved via the address range defined by the DTEA and DTSA registers and by the RC1 2 field in the DTC All eDMA initiated read write accesses that fall inside...

Page 1184: ...FIFO discards messages until it has completely emptied the queue After it is emptied an error message is queued The error encoding indicates which types of messages attempted to be queued while the F...

Page 1185: ...Nexus MPC5566 Microcontroller Reference Manual Rev 2 25 92 Freescale Semiconductor...

Page 1186: ...hanced Time Processing Unit eTPU 0xC3FC_0000 Page A 26 Peripheral Bridge B PBRIDGEB 0xFFF0_0000 Page A 35 System Bus Crossbar Switch XBAR 0xFFF0_4000 Page A 36 Error Correction Status Module ECSM 0xFF...

Page 1187: ...l bridge A off platform peripheral access control register 2 PBRIDGEA_OPACR2 32 bit Base 0x0048 Reserved Base 0x004C 0xC3F7_FFFF Frequency Modulated Phase Locked Loop FMPLL Chapter 11 Frequency Modula...

Page 1188: ...k locking register FLASH_HLR 32 bit Base 0x0008 Secondary low mid address space block locking register FLASH_SLMLR 32 bit Base 0x000C Low mid address block select register FLASH_LMSR 32 bit Base 0x001...

Page 1189: ...r 11 ADDR 15 SIU_PCR11 16 bits Base 0x0056 Pad configuration register 12 ADDR 16 SIU_PCR12 16 bits Base 0x0058 Pad configuration register 13 ADDR 17 SIU_PCR13 16 bits Base 0x005A Pad configuration reg...

Page 1190: ...R42 16 bits Base 0x0094 Pad configuration register 43 DATA 15 SIU_PCR43 16 bits Base 0x0096 Pad configuration register 44 DATA 16 SIU_PCR44 16 bits Base 0x0098 Pad configuration register 45 DATA 17 SI...

Page 1191: ...PCR74 16 bits Base 0x00D4 Pad configuration register 75 MDO 4 SIU_PCR75 16 bits Base 0x00D6 Pad configuration register 76 MDO 5 SIU_PCR76 16 bits Base 0x00D8 Pad configuration register 77 MDO 6 SIU_PC...

Page 1192: ...4 Pad configuration register 107 PCSB 2 SIU_PCR107 16 bits Base 0x0116 Pad configuration register 108 PCSB 3 SIU_PCR108 16 bits Base 0x0118 Pad configuration register 109 PCSB 4 SIU_PCR109 16 bits Bas...

Page 1193: ...IU_PCR138 16 bits Base 0x0154 Pad configuration register 139 eTPU A 25 SIU_PCR139 16 bits Base 0x0156 Pad configuration register 140 eTPU A 26 SIU_PCR140 16 bits Base 0x0158 Pad configuration register...

Page 1194: ...3 SIU_PCR170 16 bits Base 0x0194 Pad configuration register 171 eTPU B 24 SIU_PCR171 16 bits Base 0x0196 Pad configuration register 172 eTPU B 25 SIU_PCR172 16 bits Base 0x0198 Pad configuration regis...

Page 1195: ...S 23 SIU_PCR202 16 bits Base 0x01D4 Pad configuration register 203 GPIO 203 SIU_PCR203 16 bits Base 0x01D6 Pad configuration register 204 GPIO 204 SIU_PCR204 16 bits Base 0x01D8 Pad configuration regi...

Page 1196: ...ration register 258 SIU_PCR258 16 bits Base 0x0244 Pad configuration register 259 SIU_PCR259 16 bits Base 0x0246 Pad configuration register 260 SIU_PCR260 16 bits Base 0x0248 Pad configuration registe...

Page 1197: ...nfiguration register 290 SIU_PCR290 16 bits Base 0x0284 Pad configuration register 291 SIU_PCR291 16 bits Base 0x0286 Pad configuration register 292 SIU_PCR292 16 bits Base 0x0288 Pad configuration re...

Page 1198: ...2 SIU_GPDO22 8 bits Base 0x0616 GPIO pin data output register 23 SIU_GPDO23 8 bits Base 0x0617 GPIO pin data output register 24 SIU_GPDO24 8 bits Base 0x0618 GPIO pin data output register 25 SIU_GPDO2...

Page 1199: ...54 SIU_GPDO54 8 bits Base 0x0636 GPIO pin data output register 55 SIU_GPDO55 8 bits Base 0x0637 GPIO pin data output register 56 SIU_GPDO56 8 bits Base 0x0638 GPIO pin data output register 57 SIU_GPD...

Page 1200: ...SIU_GPDO86 8 bits Base 0x0656 GPIO pin data output register 87 SIU_GPDO87 8 bits Base 0x0657 GPIO pin data output register 88 SIU_GPDO88 8 bits Base 0x0658 GPIO pin data output register 89 SIU_GPDO89...

Page 1201: ...SIU_GPDO118 8 bits Base 0x0676 GPIO pin data output register 119 SIU_GPDO119 8 bits Base 0x0677 GPIO pin data output register 120 SIU_GPDO120 8 bits Base 0x0678 GPIO pin data output register 121 SIU_...

Page 1202: ...SIU_GPDO150 8 bits Base 0x0696 GPIO pin data output register 151 SIU_GPDO151 8 bits Base 0x0697 GPIO pin data output register 152 SIU_GPDO152 8 bits Base 0x0698 GPIO pin data output register 153 SIU_...

Page 1203: ...SIU_GPDO182 8 bits Base 0x06B6 GPIO pin data output register 183 SIU_GPDO183 8 bits Base 0x06B7 GPIO pin data output register 184 SIU_GPDO184 8 bits Base 0x06B8 GPIO pin data output register 185 SIU_...

Page 1204: ...3 8 bits Base 0x06D5 Reserved Base 0x06D6 0x07FF GPIO pin data input register 0 SIU_GPDI0 8 bits Base 0x0800 GPIO pin data input register 1 SIU_GPDI1 8 bits Base 0x0801 GPIO pin data input register 2...

Page 1205: ...r 31 SIU_GPDI31 8 bits Base 0x081F GPIO pin data input register 32 SIU_GPDI32 8 bits Base 0x0820 GPIO pin data input register 33 SIU_GPDI33 8 bits Base 0x0821 GPIO pin data input register 34 SIU_GPDI3...

Page 1206: ...r 63 SIU_GPDI63 8 bits Base 0x083F GPIO pin data input register 64 SIU_GPDI64 8 bits Base 0x0840 GPIO pin data input register 65 SIU_GPDI65 8 bits Base 0x0841 GPIO pin data input register 66 SIU_GPDI6...

Page 1207: ...95 8 bits Base 0x085F GPIO pin data input register 96 SIU_GPDI96 8 bits Base 0x0860 GPIO pin data input register 97 SIU_GPDI97 8 bits Base 0x0861 GPIO pin data input register 98 SIU_GPDI98 8 bits Base...

Page 1208: ...7 SIU_GPDI127 8 bits Base 0x087F GPIO pin data input register 128 SIU_GPDI128 8 bits Base 0x0880 GPIO pin data input register 129 SIU_GPDI129 8 bits Base 0x0881 GPIO pin data input register 130 SIU_GP...

Page 1209: ...9 SIU_GPDI159 8 bits Base 0x089F GPIO pin data input register 160 SIU_GPDI160 8 bits Base 0x08A0 GPIO pin data input register 161 SIU_GPDI161 8 bits Base 0x08A1 GPIO pin data input register 162 SIU_GP...

Page 1210: ...1 SIU_GPDI191 8 bits Base 0x08BF GPIO pin data input register 192 SIU_GPDI192 8 bits Base 0x08C0 GPIO pin data input register 193 SIU_GPDI193 8 bits Base 0x08C1 GPIO pin data input register 194 SIU_GP...

Page 1211: ...e 0x0988 Compare A low register SIU_CARL 32 bits Base 0x098C Compare B high register SIU_CBRH 32 bits Base 0x0990 Compare B low register SIU_CBRL 32 bits Base 0x0994 Reserved Base 0x0998 0xC3F9_FFFF E...

Page 1212: ...eTPU B time base configuration register ETPU_TBCR_B 32 bit Base 0x0040 eTPU B time base 1 ETPU_TB1R_B 32 bit Base 0x0044 eTPU B time base 2 ETPU_TB2R_B 32 bit Base 0x0048 eTPU B STAC bus interface con...

Page 1213: ...TPU A channel 0 host service request register ETPU_C0HSRR_A 32 bit Base 0x0408 Reserved Base 0x040C 0x040F eTPU A channel 1 configuration register ETPU_C1CR_A 32 bit Base 0x0410 eTPU A channel 1 statu...

Page 1214: ...0x0484 eTPU A channel 8 host service request register ETPU_C8HSRR_A 32 bit Base 0x0488 Reserved Base 0x048C 0x048F eTPU A channel 9 configuration register ETPU_C9CR_A 32 bit Base 0x0490 eTPU A channe...

Page 1215: ...it Base 0x0504 eTPU A channel 16 host service request register ETPU_C16HSRR_A 32 bit Base 0x0508 Reserved Base 0x050C 0x050F eTPU A channel 17 configuration register ETPU_C17CR_A 32 bit Base 0x0510 eT...

Page 1216: ...it Base 0x0584 eTPU A channel 24 host service request register ETPU_C24HSRR_A 32 bit Base 0x0588 Reserved Base 0x058C 0x058F eTPU A channel 25 configuration register ETPU_C25CR_A 32 bit Base 0x0590 eT...

Page 1217: ...0SCR_B 32 bit Base 0x0804 eTPU B channel 0 host service request register ETPU_C0HSRR_B 32 bit Base 0x0808 Reserved Base 0x080C 0x080F eTPU B channel 1 configuration register ETPU_C1CR_B 32 bit Base 0x...

Page 1218: ...e 0x0884 eTPU B channel 8 host service request register ETPU_C8HSRR_B 32 bit Base 0x0888 Reserved Base 0x088C 0088F eTPU B channel 9 configuration register ETPU_C9CR_B 32 bit Base 0x0890 eTPU B channe...

Page 1219: ...it Base 0x0904 eTPU B channel 16 host service request register ETPU_C16HSRR_B 32 bit Base 0x0908 Reserved Base 0x090C 0x090F eTPU B channel 17 configuration register ETPU_C17CR_B 32 bit Base 0x0910 eT...

Page 1220: ...it Base 0x0984 eTPU B channel 24 host service request register ETPU_C24HSRR_B 32 bit Base 0x0988 Reserved Base 0x098C 0x098F eTPU B channel 25 configuration register ETPU_C25CR_B 32 bit Base 0x0990 eT...

Page 1221: ...ost service request register ETPU_C31HSRR_B 32 bit Base 0x09F8 Reserved Base 0x09FC 0x7FFF Shared data memory parameter RAM SDM 3 KB Base 0x8000 0x8BFF Reserved Base 0x8C00 0xBFFF SDM PSE mirror Base...

Page 1222: ...purpose control register 1 XBAR_SGPCR1 32 bit Base 0x0110 Reserved Base 0x0114 0x02FF Master priority register 3 XBAR_MPR3 32 bit Base 0x0300 Reserved Base 0x0304 0x030F Slave general purpose control...

Page 1223: ...r ECSM_FEAT 8 bit Base 0x0057 Flash ECC data register high ECSM_FEDRH 32 bit Base 0x0058 Flash ECC data register low ECSM_FEDRL 32 bit Base 0x005C RAM ECC address register ECSM_REAR 32 bit Base 0x0060...

Page 1224: ...nel priority register 2 EDMA_CPR2 8 bit Base 0x0102 Channel priority register 3 EDMA_CPR3 8 bit Base 0x0103 Channel priority register 4 EDMA_CPR4 8 bit Base 0x0104 Channel priority register 5 EDMA_CPR...

Page 1225: ...gister 33 EDMA_CPR33 8 bit Base 0x0121 Channel priority register 34 EDMA_CPR34 8 bit Base 0x0122 Channel priority register 35 EDMA_CPR35 8 bit Base 0x0123 Channel priority register 36 EDMA_CPR36 8 bit...

Page 1226: ...ster 1 TCD1 256 bit Base 0x1020 Transfer control descriptor register 2 TCD2 256 bit Base 0x1040 Transfer control descriptor register 3 TCD3 256 bit Base 0x1060 Transfer control descriptor register 4 T...

Page 1227: ...r 32 TCD32 256 bit Base 0x1400 Transfer control descriptor register 33 TCD33 256 bit Base 0x1420 Transfer control descriptor register 34 TCD34 256 bit Base 0x1440 Transfer control descriptor register...

Page 1228: ...D62 256 bit Base 0x17C0 Transfer control descriptor register 63 TCD63 256 bit Base 0x17E0 Reserved Base 0x1800 0xFFF4_7FFF Interrupt Controller INTC Chapter 10 Interrupt Controller INTC 0xFFF4_8000 Mo...

Page 1229: ...R12 8 bit Base 0x004C Priority select register 13 INTC_PSR13 8 bit Base 0x004D Priority select register 14 INTC_PSR14 8 bit Base 0x004E Priority select register 15 INTC_PSR15 8 bit Base 0x004F Priorit...

Page 1230: ...egister 44 INTC_PSR44 8 bit Base 0x006C Priority select register 45 INTC_PSR45 8 bit Base 0x006D Priority select register 46 INTC_PSR46 8 bit Base 0x006E Priority select register 47 INTC_PSR47 8 bit B...

Page 1231: ...egister 76 INTC_PSR76 8 bit Base 0x008C Priority select register 77 INTC_PSR77 8 bit Base 0x008D Priority select register 78 INTC_PSR78 8 bit Base 0x008E Priority select register 79 INTC_PSR79 8 bit B...

Page 1232: ...8 INTC_PSR108 8 bit Base 0x00AC Priority select register 109 INTC_PSR109 8 bit Base 0x00AD Priority select register 110 INTC_PSR110 8 bit Base 0x00AE Priority select register 111 INTC_PSR111 8 bit Bas...

Page 1233: ...ter 140 INTC_PSR140 8 bit Base 0x00CC Priority select register 141 INTC_PSR141 8 bit Base 0x00CD Priority select register 142 INTC_PSR142 8 bit Base 0x00CE Priority select register 143 INTC_PSR143 8 b...

Page 1234: ...ter 172 INTC_PSR172 8 bit Base 0x00EC Priority select register 173 INTC_PSR173 8 bit Base 0x00ED Priority select register 174 INTC_PSR174 8 bit Base 0x00EE Priority select register 175 INTC_PSR175 8 b...

Page 1235: ...ter 204 INTC_PSR204 8 bit Base 0x010C Priority select register 205 INTC_PSR205 8 bit Base 0x010D Priority select register 206 INTC_PSR206 8 bit Base 0x010E Priority select register 207 INTC_PSR207 8 b...

Page 1236: ...ter 236 INTC_PSR236 8 bit Base 0x012C Priority select register 237 INTC_PSR237 8 bit Base 0x012D Priority select register 238 INTC_PSR238 8 bit Base 0x012E Priority select register 239 INTC_PSR239 8 b...

Page 1237: ...ter 268 INTC_PSR268 8 bit Base 0x014C Priority select register 269 INTC_PSR269 8 bit Base 0x014D Priority select register 270 INTC_PSR270 8 bit Base 0x014E Priority select register 271 INTC_PSR271 8 b...

Page 1238: ...r 299 INTC_PSR299 8 bit Base 0x016B Priority select register 300 INTC_PSR300 8 bit Base 0x016C Fast Ethernet Controller FEC Chapter 15 Fast Ethernet Controller FEC 0xFFF4_C000 Interrupt event register...

Page 1239: ...ase 0x0000 Reserved Base 0x0004 0x0007 Null message send format register EQADC_NMSFR 32 bit Base 0x0008 External trigger digital filter register EQADC_ETDFR 32 bit Base 0x000C CFIFO push register 0 EQ...

Page 1240: ...Base 0x0070 FIFO and interrupt status register 1 EQADC_FISR1 32 bit Base 0x0074 FIFO and interrupt status register 2 EQADC_FISR2 32 bit Base 0x0078 FIFO and interrupt status register 3 EQADC_FISR3 32...

Page 1241: ...ster 3 EQADC_CF1R3 32 bit Base 0x014C Reserved Base 0x0150 0x017F CFIFO 2 register 0 EQADC_CF2R0 32 bit Base 0x0180 CFIFO 2 register 1 EQADC_CF2R1 32 bit Base 0x0184 CFIFO 2 register 2 EQADC_CF2R2 32...

Page 1242: ...32 bit Base 0x0348 RFIFO 1 register 3 EQADC_RF1R3 32 bit Base 0x034C Reserved Base 0x0350 0x037F RFIFO 2 register 0 EQADC_RF2R0 32 bit Base 0x0380 RFIFO 2 register 1 EQADC_RF2R1 32 bit Base 0x0384 RFI...

Page 1243: ...0 DSPI C 0xFFF9_C000 DSPI D Module configuration register DSPIx_MCR 32 bit Base 0x0000 Reserved Base 0x0004 0x0007 Transfer count register DSPIx_TCR 32 bit Base 0x0008 Clock and transfer attribute reg...

Page 1244: ...MPR 32 bit Base 0x00C8 DSI deserialization data register DSPIx_DDR 32 bit Base 0x00CC Reserved Base 0x00D0 0xFFF9_3FFF DSPI A 0xFFF9_7FFF DSPI B 0xFFF9_BFFF DSPI C 0xFFFA_FFFF DSPI D Enhanced Serial C...

Page 1245: ...ster high CANx_IFRH 32 bit Base 0x002C Interrupt flag register low CANx_IFRL 32 bit Base 0x0030 Reserved Base 0x0034 0x007F Boot Assist Module BAM Chapter 15 Boot Assist Module BAM 0xFFFF_C000 Reserve...

Page 1246: ...Base 0x0240 Message buffer 29 MB29 16 bit Base 0x0250 Message buffer 30 MB30 16 bit Base 0x0260 Message buffer 31 MB31 16 bit Base 0x0270 Message buffer 32 MB32 16 bit Base 0x0280 Message buffer 33 M...

Page 1247: ...uffer 62 MB62 16 bit Base 0x0460 Message buffer 63 MB63 16 bit Base 0x0470 Reserved Base 0x0500 end 1 The registers mapped in the ECSM module 0xFFF4_0014 0xFFF4_001F can control and configure the soft...

Page 1248: ...re Register 1 575 ESR Exception Syndrome Register 62 MCSR Machine Check Syndrome Register 572 DEAR Data Exception Address Register 61 IVPR Interrupt Vector Prefix Register 63 IVOR1 Interrupt Vector Of...

Page 1249: ...Time Base Upper Register 285 TCR Timer Control Register 340 TSR Timer Status Register 336 DEC Decrementer Register 22 DECAR Decrementer Auto reload Register 54 Debug Registers DBCR0 Debug Control Regi...

Page 1250: ...Control and Status Register 0 1010 L1FINV0 L1 Cache Flush and Invalidate Control Register 0 1016 APU Registers SPEFSCR SPE APU Status and Control Register 512 Table A 4 e200z6 Core SPR Numbers User Mo...

Page 1251: ...66 Freescale Semiconductor TBU Time Base Upper Register 269 Cache Registers L1CFG0 L1 Cache Configuration Register 515 APU Registers SPEFSCR SPE APU Status and Control Register 512 Table A 4 e200z6 C...

Page 1252: ...libration assembled devices is detailed in Figure B 1 Freescale produced VertiCal bases use the calibration assembled MPC5500 device mounted on a small circuit board with a footprint which is compatib...

Page 1253: ...on Assembly Figure B 2 VertiCal Base VertiCal compliant top board VertiCal base Application production PCB VertiCal connector system Calibration packaged MPC5500 device Production packaged sized 23mm...

Page 1254: ...0 3 chip selects have multiplexed signal functions to provide additional addressing bits that allows the flexibility of increasing the addressing range or the number of chip selects The calibration fu...

Page 1255: ...his transaction is targeted for a particular calibration memory bank The calibration chip selects are driven by the EBI CAL_CS n is driven in the same clock as the assertion of TS and valid address an...

Page 1256: ...than can be connected to the balls on a 416 pin package Therefore the die is assembled in a 496 pin chip scale package CSP and this package is used in the VertiCal base assembly B 6 Power Supplies The...

Page 1257: ...Top Board is added onto the VertiCal connector This allows the engine calibrator to modify settings in SRAM possibly using the Nexus interface or even by using the SCI port or a CAN interface Refer to...

Page 1258: ...programming mode to support rapid end of line programming Added page footnote to read Although this device has a maximum of 329 interrupts the logic requires that the total number of interrupts be div...

Page 1259: ...cal assembly has ball connections for all the available signals on the device Added to Table 2 1 MPC5566 Signal Properties a footnote to PLLCFG 2 PLLCFG 2 must be tied to ground Added TXDA as an alter...

Page 1260: ...register diagrams for the following PCRs PCR122 PCR124 PCR127 PCR133 PCR199 PCR200 Reversed register addresses in register diagrams for PCR225 PCR220 Chapter 7 Crossbar Switch Added to Register Descr...

Page 1261: ...dlines that share a resource They can be placed at the same priority without any further priority inversion and they do not need to use the PCP to access the shared resource To Reducing the number of...

Page 1262: ...t code for the mtlr r3 code line to move the INTC_IACKR address into the link register Chapter 11 Frequency Modulated Phase Locked Loop and System Clock Section FMPLL Calibration Routine Corrected the...

Page 1263: ...aph from Table 12 18 shows the allowed sizes that an internal or external master can request from the EBI The behavior of the EBI for request sizes not shown below is undefined No error signal is asse...

Page 1264: ...moved the words or be driven by from the sentence FROM The TCRs drive or be driven by an eMIOS time base through the shared time and counter STAC bus or they be written by eTPU function software TO It...

Page 1265: ...use with AM 1 Moved table note into AM 1 column Chapter 20 Deserial Serial Peripheral Interface Changed the NOTE in the DSPI_PUSHR register From Only the TXDATA field is used for slaves To TXDATA is...

Page 1266: ...s Appendix B Calibration Added footnote to the following signals in the Calibration Bus Signals table WE BE 2 3 ADDR 8 11 TEA The footnote reads Not available on the 324 package Removed the reference...

Page 1267: ...MPC5566 Reference Manual Revision History MPC5566 Microcontroller Reference Manual Rev 2 Freescale Semiconductor C 10...

Page 1268: ...MPC5566 Reference Manual Revision History MPC5566 Microcontroller Reference Manual Rev 2 Freescale Semiconductor C 11...

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