NXP Semiconductors MPC5566, Reference Manual

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Introduction
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 1-9
— Word length programmable as 8 or 9 bits
— Separately enabled transmitter and receiver
— LIN support
— DMA support
— Interrupt request support
• Four FlexCANs
— 64 message buffers each
— Full implementation of the CAN protocol specification, Version 2.0B
— Based on and including all existing features of the Freescale TouCAN module
— Programmable acceptance filters
— Individual receive filtering per message buffer
— Short latency time for high-priority transmit messages
— Arbitration scheme according to message ID or message buffer number
— Listen-only mode capabilities
— Programmable clock source: system clock or oscillator clock
— Reception queue possible by setting more than one receive message buffer with the same ID
— Backwards compatibility with previous FlexCAN modules
• Nexus development interface (NDI)
— Per IEEE
®
-ISTO 5001-2003
— Real-time development support for Power Architecture core and the eTPU engines through
Nexus class 3 (some class 4 support)
— Data trace of eDMA accesses
— Read and write access
— Configured via the IEEE
®
1149.1 (JTAG) port
— High-bandwidth mode for fast message transmission
— Reduced bandwidth mode for reduced pin usage
• IEEE
®
1149.1 JTAG controller (JTAGC)
— IEEE
®
1149.1-2001 test access port (TAP) interface
— JCOMP input that provides the ability to share the TAP; selectable modes of operation include
JTAGC/debug or normal system operation
— 5-bit instruction register that supports IEEE
®
1149.1-2001 defined instructions
— 5-bit instruction register that supports additional public instructions
— Three test data registers: a bypass register, a boundary scan register, and a device identification
register
— TAP controller state machine that controls the operation of the data registers, instruction
register and associated circuitry