NXP Semiconductors MPC5566, Reference Manual

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External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
12-18 Freescale Semiconductor
12.3.1.6 EBI Base Registers 0–3 (EBI_BR n )
and EBI Calibration Base Registers 0–3 (EBI_CAL_BR n )
The EBI_BR n are used to define the base address and other attributes for the corresponding chip select.
The EBI_CAL_BR n are used to define the base address and other attributes for the corresponding
calibration chip select.
24
BME
Bus monitor enable. Controls whether the bus monitor is enabled for internal to external bus cycles. Regardless of
the BME value, the bus monitor is always disabled for chip select accesses, since these always use internal TA and
thus have no danger of hanging the system.
0 Disable bus monitor
1 Enable bus monitor (for non-chip select accesses only)
25–31 Reserved.
Address: Base + 0x0010 (EBI_BR0)
Base + 0x0018 (EBI_BR1)
Base + 0x0020 (EBI_BR2)
Base + 0x0028 (EBI_BR3)
Base + 0x0040 (EBI_CAL_BR0)
Base + 0x0048 (EBI_CAL_BR1)
Base + 0x0050 (EBI_CAL_BR2)
Base + 0x0058 (EBI_CAL_BR3)
Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 1
BA
W
Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BA
0 0 0
PS
0 0 0 0
BL WEBS TBDIP
0 0
BI V
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Figure 12-5. EBI Base Registers 0–3 (EBI_BR n ) and EBI Calibration Base Registers 0–3 (EBI_CAL_BR n )
Table 12-9. EBI_BMCR Field Descriptions (continued)
Field Description