NXP Semiconductors MPC5566, Reference Manual

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System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
6-16 Freescale Semiconductor
The following table describes the fields in the external interrupt status register:
6.3.1.5 DMA Interrupt Request Enable Register (SIU_DIRER)
The SIU_DIRER asserts a DMA transfer or external interrupt request if the IRQ flag bit is set in the
SIU_EISR. The DMA transfer or external interrupt request enable bits (EIRE flags) enable an external
interrupt request or DMA transfer request. The SIU uses one interrupt request to the interrupt controller.
The EIRE bits determine the external interrupt requests that assert the SIU interrupt request to the interrupt
controller.
Address: Base + 0x0014 Access: R/w1c
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R EIF15 EIF14 EIF13 EIF12 EIF11 EIF10 EIF9 EIF8 EIF7 EIF6 EIF5 EIF4 EIF3 EIF2 EIF1 EIF0
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 6-5. External Interrupt Status Register (SIU_EISR)
Table 6-11. SIU_EISR Field Descriptions
Field Description
0–15 Reserved
16–31
EIF n
External interrupt request flag n. This bit is set when an edge-triggered event occurs on the corresponding IRQ[ n ]
input. Cleared by writing a 1.
0 No edge-triggered event has occurred on the corresponding IRQ[
n ] input.
1 An edge-triggered event has occurred on the corresponding IRQ[ n ] input.
Address: Base + 0x0018 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R EIRE
15
EIRE
14
EIRE
13
EIRE
12
EIRE
11
EIRE
10
EIRE
9
EIRE
8
EIRE
7
EIRE
6
EIRE
5
EIRE
4
EIRE
3
EIRE
2
EIRE
1
EIRE
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 6-6. DMA Interrupt Request Enable Register (SIU_DIRER)