NXP Semiconductors MPC5566, Reference Manual

Page: 767 / 1268

Enhanced Time Processing Unit (eTPU)
MPC5566 Microcontroller Reference Manual, Rev. 2
18-10 Freescale Semiconductor
— Global parameter address mode allows access to common channel data of up to 256 32-bit
parameters (1024 bytes).
— Support for indirect and stacked data access schemes.
— Parallel execution of: data access, ALU, channel control and flow control subinstructions in
selected combinations.
— 24-bit registers and ALU, plus one 32-bit register for full-width SDM access.
— Additional 24-bit multiply/MAC/divide unit which supports all signed/unsigned/
multiply/MAC combinations, and unsigned 24-bit divide. The MAC/divide unit works in
parallel with the regular microcode commands.
• Resource sharing features resolve channel contention for common use of channel registers,
memory and microengine time
— Hardware scheduler works as a ‘task management’ unit, dispatching event service routines by
predefined, host-configured priority.
— Hardware breakpoints on data access, qualified by address and/or data values.
— Hardware breakpoints on instruction address.
— Automatic channel context switch when a ‘task switch’ occurs; that is, one function thread ends
and another begins to service a request from another channel. Channel-specific registers, flags
and parameter base address are automatically loaded for the next serviced channel.
— Individual channel priority setting in three levels: high, middle, and low.
— Scheduler priority scheme allows calculation of worst case latency for event servicing and
ensures servicing of all channels by preventing permanent blockage.
— SDM shared between host core and both eTPU engines, supporting channel-channel or
host-channel communication.
— Hardware implementation of four semaphores allows for resource arbitration between channels
in both eTPU engines.
— Hardware semaphores are directly supported by the microengine instruction set.
— Dual-parameter coherency hardware support allows coherent (to host) access to two
parameters by microengines in back-to-back accesses, or by Host CPU in 64-bit accesses.
— Coherent dual-parameter controller allows coherent (to microengines) accesses to two
parameters by the host.
• Test and development support features
— Nexus level 3 debug support through the eTPU Nexus block (NDEDI)
— Software breakpoints
— SCM (code memory) continuous signature-check built-in code integrity test multiple input
signature calculator (MISC): runs concurrently with eTPU normal operation
18.2 Modes of Operation
The eTPU is capable of working in the following modes.