NXP Semiconductors MPC5566, Reference Manual

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Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 15-21
15.3.4.2.10 Transmit Control Register (TCR)
The transmit control register is read/write and is used to configure the transmit block. This register is
cleared at system reset. Modify bits 29 and 30 only when ECR[ETHER_EN] = 0.
Table 15-14 describes the fields and functions in the transmit control register:
Address: Base + 0x00C4 Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 RFC_
PAUSE
TFC_
PAUSE
FDEN HBC GTS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 15-12. Transmit Control Register (TCR)
Table 15-14. Transmit Control Register Field Descriptions
Field Description
0–26 Reserved, must be cleared.
27
RFC_PAUSE
Receive frame control pause. This read-only status bit is asserted when a full duplex flow control pause
frame has been received and the transmitter is paused for the duration defined in this pause frame. This
bit automatically clears when the pause duration is complete.
28
TFC_PAUSE
Transmit frame control pause. Transmits a PAUSE frame when asserted. When this bit is set, the MAC
stops transmitting data frames after the current transmission completes. At this time, the GRA interrupt in
the EIR register is asserted. With transmission of data frames stopped, the MAC transmits a MAC Control
PAUSE frame. Next, the MAC clears the TFC_PAUSE bit and resumes transmitting data frames. If you
pause the transmitter by asserting GTS or receiving another PAUSE frame, the MAC can still transmit a
MAC control PAUSE frame.
29
FDEN
Full duplex enable. If set, frames are transmitted independent of carrier sense and collision inputs. This
bit must only be modified when ETHER_EN is deasserted.
30
HBC
Heartbeat control. If set, the heartbeat check is performed following end of transmission and the HB bit in
the status register is set if the collision input does not assert within the heartbeat window. This bit must
only be modified when ETHER_EN is deasserted.
31
GTS
Graceful transmit stop. When this bit is set, the MAC stops transmitting after any frame that is currently
being transmitted is complete and the GRA interrupt in the EIR register is asserted. If frame transmission
is not currently underway, the GRA interrupt is asserted immediately. Once transmission has completed,
a “restart” can be accomplished by clearing the GTS bit. The next frame in the transmit FIFO is then
transmitted. If an early collision occurs during transmission when GTS = 1, transmission stops after the
collision. The frame is transmitted again once GTS is cleared. Previous frames can reside in the transmit
FIFO that are transmitted when GTS is reasserted. To avoid this condition, deassert ECR[ETHER_EN]
following the GRA interrupt.