MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
25-1
Chapter 25
Nexus Development Interface
25.1
Introduction
The device microcontroller contains multiple Nexus clients that communicate over a single IEEE
®
-ISTO
5001™-2003 Nexus class 3 combined JTAG IEEE
®
1149.1/auxiliary out interface. Combined, all of the
Nexus clients are referred to as the Nexus development interface (NDI). Class 3 Nexus allows for program,
data, and ownership trace of the microcontroller execution without access to the external data and address
buses.
This chapter is organized in the following manner:
•
The chapter opens with sections that provide a high level view of the Nexus development interface:
Section 25.8, “NPC Initialization/Application Information
The remainder of the chapter contains sections that discuss the remaining modules of the Nexus
development interface:
•
Nexus dual-eTPU development interface (NDEDI). The device has two eTPU engines. Refer to
Section 25.9, “Nexus Dual eTPU Development Interface (NDEDI)
” and the
eTPU Reference
Manual
for information about the NDEDI.
•
Nexus e200z6 core interface (NZ6C3). In this chapter, the NZ6C3 interface is discussed in
Section 25.10, “e200z6 Class 3 Nexus Module (NZ6C3)
.”
•
Nexus crossbar eDMA interface (NXDM). Refer to
Section 25.15, “Nexus Crossbar eDMA
.”
Communication to the NDI is handled via the auxiliary port and the JTAG port.
•
The auxiliary port is comprised of nine or 17 output pins and 1 input pin. The output pins include
one message clock out (MCKO) pin, four or 12 message data out (MDO) pins, two message
start/end out (MSEO) pins, one ready (RDY) pin, and one event out (EVTO) pin. Event in (EVTI)
is the only input pin for the auxiliary port.
•
The JTAG port consists of four inputs and one output. These pins include JTAG compliance select
(JCOMP), test data input (TDI), test data output (TDO), test mode select (TMS), and test clock
input (TCK). TDI, TDO, TMS, and TCK are compliant with the IEEE
®
1149.1-2001 standard and
are shared with the NDI through the test access port (TAP) interface. JCOMP along with power-on
reset and the TAP state machine are used to control reset for the NDI module. Ownership of the
TAP is achieved by loading the appropriate enable instruction for the desired Nexus client in the
JTAG controller (JTAGC) when JCOMP is asserted. Refer to
for the JTAGC opcodes
to access the different Nexus clients.
Summary of Contents for MPC5566
Page 81: ...Introduction MPC5566 Microcontroller Reference Manual Rev 2 1 24 Freescale Semiconductor...
Page 135: ...Signal Description MPC5566 Microcontroller Reference Manual Rev 2 2 54 Freescale Semiconductor...
Page 189: ...Reset MPC5566 Microcontroller Reference Manual Rev 2 4 20 Freescale Semiconductor...
Page 603: ...Flash Memory MPC5566 Microcontroller Reference Manual Rev 2 13 38 Freescale Semiconductor...
Page 609: ...SRAM MPC5566 Microcontroller Reference Manual Rev 2 14 6 Freescale Semiconductor...
Page 1073: ...MPC5566 Microcontroller Reference Manual Rev 2 22 36 Freescale Semiconductor...
Page 1185: ...Nexus MPC5566 Microcontroller Reference Manual Rev 2 25 92 Freescale Semiconductor...
