NXP Semiconductors MPC5566, Reference Manual

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Error Correction Status Module (ECSM)
MPC5566 Microcontroller Reference Manual, Rev. 2
8-4 Freescale Semiconductor
8.2.1.3 ECC Configuration Register (ECSM_ECR)
ECSM_ECR is an 8-bit control register that enables or disables ECC error reporting during RAM and flash
accesses. In addition to the interrupt generation, the ECSM captures specific information (memory
address, attributes and data, bus master number, etc.) that is useful for failure analysis.
The ECC reporting logic can detect non-correctable memory errors. When a non-correctable error
terminates the current access to the flash memory or RAM, an error condition is generated. In many cases,
the error termination is reported directly by the initiating bus master.
The following table describes the fields in the error configuration register:
8.2.1.4 ECC Status Register (ECSM_ESR)
The ECC status register (ECSM_ESR) is an 8-bit control register that defines the types of ECC events
detected. The ESR indicates the last, correctly-enabled memory event detected. The ECSM ECC interrupt
request is generated as defined by the boolean equation:
ECSM_ECC_IRQ
= ECSM_ECR[ERNCR] & ECSM_ESR[RNCE] // ram, noncorrectable error
| ECSM_ECR[EFNCR] & ECSM_ESR[FNCE] // flash, noncorrectable error
where the combination of the following criteria generates the interrupt request:
• Correctly-enabled category in the ECSM_ECR; and
• Condition in the ECSM_ESR detected.
Base (0xFFF4_0000) + 0x0043 Access: Read/Write
0 1 2 3 4 5 6 7
R 0 0 0 0 0 0
ERNCR EFNCR
W
Reset 0 0 0 0 0 0 0 0
Figure 8-1. ECC Configuration Register (ECSM_ECR)
Table 8-2. ECSM_ECR Field Definitions
Field Description
0–5 Reserved.
6
ERNCR
Enable RAM non-correctable reporting. The occurrence of a non-correctable multi-bit RAM error generates a ECSM
ECC interrupt request by the asserting the ECSM_ESR[RNCE]. The faulting address, attributes and data are also
captured in the REAR, REMR, REAT and REDR registers.
0 Reporting of non-correctable RAM errors is disabled.
1 Reporting of non-correctable RAM errors is enabled.
7
EFNCR
Enable flash non-correctable reporting. The occurrence of a non-correctable multi-bit flash error generates a ECSM
ECC interrupt request as signalled by the assertion of ECSM_ESR[FNCE]. The faulting address, attributes and data
are also captured in the FEAR, FEMR, FEAT and FEDR registers.
0 Reporting of non-correctable flash errors is disabled.
1 Reporting of non-correctable flash errors is enabled.