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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-72
Freescale Semiconductor
19.4.3.6
CFIFO and Trigger Status
19.4.3.6.1
CFIFO Operation Status
Each CFIFO has its own CFIFO status field. CFIFO status (CFS) can be read from EQADC_CFSSR (refer
to
Section 19.3.2.11, “eQADC CFIFO Status Register (EQADC_CFSR)
indicate the CFIFO status switching condition. Refer to
for the meaning of each CFIFO
operation status. The last CFIFO to transfer a command to an on-chip ADC can be read from the LCFT
n
(
n
Section 19.3.2.10, “eQADC CFIFO Status Snapshot Registers 0–2
.” The last CFIFO to transfer a command to a specific external command buffer can
be identified by reading the EQADC_CFSSR
n
[LCFTSSI] and EQADC_CFSSR
n
[ENI] fields (see
Section 19.3.2.10, “eQADC CFIFO Status Snapshot Registers 0–2 (EQADC_CFSSRn)
.”
Continuous
Scan Edge
No
A corresponding edge
occurs.
Yes
Yes
None.
Continuous
Scan Level
No
Gate is opened.
No
No
The eQADC also stops transfers
from the CFIFO when CFIFO
status changes from triggered
due to the detection of a closed
gate.
1
Refer to
Section 19.4.3.6.2, “Command Queue Completion Status
for more information on EOQ.
2
Refer to
Section 19.4.3.6.3, “Pause Status
,” for more information on pause.
3
The eQADC always stops command transfers from a CFIFO when the CFIFO operation mode is disabled.
4
The eQADC always stops command transfers from a CFIFO when a higher priority CFIFO is triggered. Refer to
Section 19.4.3.2, “CFIFO Prioritization and Command Transfer
,” for information on CFIFO priority.
5
If a closed gate is detected while no command transfers are taking place, it has an immediate effect on the CFIFO
status. If a closed gate is detected during the serial transmission of a command to the external device, it has no effect
on the CFIFO status until the transmission completes.
Table 19-44. CFIFO Scan Trigger Mode—Command Transfer Start/Stop Summary
Trigger Mode
Requires
Asserted SSS
to Recognize
Trigger
Events?
Command Transfer
Start/Restart Condition
Stop on
asserted
EOQ
bit
1
?
Stop on
asserted
Pause
bit
2
?
Other Command Transfer Stop
Condition
3
4
Summary of Contents for MPC5566
Page 81: ...Introduction MPC5566 Microcontroller Reference Manual Rev 2 1 24 Freescale Semiconductor...
Page 135: ...Signal Description MPC5566 Microcontroller Reference Manual Rev 2 2 54 Freescale Semiconductor...
Page 189: ...Reset MPC5566 Microcontroller Reference Manual Rev 2 4 20 Freescale Semiconductor...
Page 603: ...Flash Memory MPC5566 Microcontroller Reference Manual Rev 2 13 38 Freescale Semiconductor...
Page 609: ...SRAM MPC5566 Microcontroller Reference Manual Rev 2 14 6 Freescale Semiconductor...
Page 1073: ...MPC5566 Microcontroller Reference Manual Rev 2 22 36 Freescale Semiconductor...
Page 1185: ...Nexus MPC5566 Microcontroller Reference Manual Rev 2 25 92 Freescale Semiconductor...