NXP Semiconductors MPC5566, Reference Manual

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MPC5566 Microcontroller Reference Manual, Rev. 2
22-22 Freescale Semiconductor
22.3.3.8 Interrupt Masks High Register (ICAN x _IMRH)
CAN x _IMRH allows any number of a range of 32 message buffer interrupts to be enabled or disabled. It
contains one interrupt mask bit per buffer, enabling the CPU to determine which buffer generates an
interrupt after a successful transmission or reception (that is, when the corresponding IFRH bit is set).
22.3.3.9 Interrupt Masks Low Register (CAN x _IMRL)
CAN x _IMRL allows enabling or disabling any number of a range of 32 message buffer interrupts. It
contains one interrupt mask bit per buffer, enabling the CPU to determine which buffer generates an
interrupt after a successful transmission or reception (that is, when the corresponding IFRL bit is set).
30
ERRINT
Error interrupt. This status bit indicates that at least one of the error bits (bits 16-21) is set. If
CAN
x _CR[ERRMSK] is set, an interrupt is generated to the CPU. This bit is cleared by writing it to 1.
Writing 0 has no effect.
0 No such occurrence
1 Indicates setting of any error bit in the CAN
x _ESR
31 Reserved.
Address: Base + 0x0024 Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R BUF
63M
BUF
62M BUF
61M BUF
60M BUF
59M BUF
58M BUF
57M BUF
56M BUF
55M BUF
54M BUF
53M BUF
52M BUF
51M BUF
50M BUF
49M BUF
48M
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R BUF
47M
BUF
46M BUF
45M BUF
44M BUF
43M BUF
42M BUF
41M BUF
40M BUF
39M BUF
38M BUF
37M BUF
36M BUF
35M BUF
34M BUF
33M BUF
32M
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 22-10. Interrupt Masks High Register (CAN x _IMRH)
Table 22-13. CAN x _IMRH Field Descriptions
Field Description
0–31
BUF n M
Message buffer n mask. Enables or disables the respective FlexCAN2 message buffer (MB63 to MB32)
Interrupt.
0 The corresponding buffer Interrupt is disabled
1 The corresponding buffer Interrupt is enabled
Note: Setting or clearing a bit in the IMRH register can assert or negate an interrupt request, respectively.
Table 22-12. CAN x _ESR Field Descriptions (continued)
Field Description