NXP Semiconductors MPC5566, Reference Manual

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Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
17-38 Freescale Semiconductor
The counter clock (an input event) is triggered by a rising or falling edge, or by both the rising and falling
edges on the input pin. The polarity of the triggering edge is selected by the EDSEL and EDPOL bits in
EMIOS_CCR
n .
For continuous operating mode (MODE[6] cleared), the counter is cleared on the next input event after a
FLAG generation and continues to operate as described above.
For single shot operation (MODE[6] set), the counter is not cleared or incremented after a FLAG
generation, until a new writing operation to register A is performed.
NOTE
The FORCMA and FORCMB bits have no effect when the unified channel
is configured for PEA mode.
Figure 17-25 and Figure 17-26 show how the unified channel can be used for continuous and single shot
pulse/edge accumulation mode.
Figure 17-25. Pulse/Edge Accumulation Continuous Mode Example
Selected
counter bus
0x000090 0x000400 0x001000 0x007000
0x001500
Input signal
2
A2 value
4
0x001500
0xxxxxxx 0x007000 0x000400
0xxxxxxx 0x001000 0x000090
0xFFFFFF
0x001500
EMIOS_CCNTR n
1
FLAG
set event
MODE[6] = 0
Write to A1 A1 match A1 match
A1 value
3
B1 value
Notes:
1
Cleared on the first input event after writing to register A1.
2
After input filter.
0xxxxxxx 0x000090 0x007000 0x001000
3
Writing EMIOS_CADR n writes to A1.
B2 value
5
0x000400
Time
Events A1 events No events A1 events
4
Reading EMIOS_CADR n returns the value of A2.
5
Reading EMIOS_CBDR n returns the value of B1.
0x000000
0xxxxxxx 0x001500