NXP Semiconductors MPC5566, Reference Manual

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IEEE 1149.1 Test Access Port Controller (JTAGC)
MPC5566 Microcontroller Reference Manual, Rev. 2
24-8 Freescale Semiconductor
24.4.3.1 Enabling the TAP Controller
The JTAGC TAP controller is enabled by setting JCOMP to a logic 1 value.
24.4.3.2 Selecting an IEEE 1149.1-2001 Register
Access to the JTAGC data registers is done by loading the instruction register with any of the JTAGC
instructions while the JTAGC is enabled. Instructions are shifted in via the select-IR-scan path and loaded
in the update-IR state. At this point, all data register access is performed via the select-DR-scan path.
The select-DR-scan path is used to read or write the register data by shifting in the data (LSB first) during
the shift-DR state. When reading a register, the register value is loaded into the IEEE 1149.1-2001 shifter
during the capture-DR state. When writing a register, the value is loaded from the IEEE 1149.1-2001
shifter to the register during the update-DR state. When reading a register, there is no requirement to shift
out the entire register contents. Shifting can be terminated after fetching the required number of bits.
24.4.4 JTAGC Instructions
This section gives an overview of each instruction, refer to the IEEE 1149.1-2001 standard for more
details.
The JTAGC implements the IEEE 1149.1-2001 defined instructions listed in Table 24-3 .
Table 24-3. JTAG Instructions
Instruction Code[4:0] Instruction Summary
IDCODE 00001 Selects device identification register for shift
SAMPLE/PRELOAD 00010 Selects boundary scan register for shifting, sampling, and preloading without
disturbing functional operation
SAMPLE 00011 Selects boundary scan register for shifting and sampling without disturbing
functional operation
EXTEST 00100 Selects boundary scan register while applying preloaded values to output
pins and asserting functional reset
HIGHZ 01001 Selects bypass register while three-stating all output pins and asserting
functional reset
CLAMP 01100 Selects bypass register while applying preloaded values to output pins and
asserting functional reset
ACCESS_AUX_TAP_NPC 10000 Grants the Nexus port controller (NPC) ownership of the TAP
ACCESS_AUX_TAP_ONCE 10001 Grants the Nexus e200z6 core interface (NZ6C3) ownership of the TAP
ACCESS_AUX_TAP_eTPU 10010 Grants the Nexus dual-eTPU development interface (NDEDI) ownership of
the TAP
ACCESS_AUX_TAP_DMA 10011 Grants the Nexus crossbar DMA interface (NXDM) ownership of the TAP
BYPASS 11111 Selects bypass register for data operations