NXP Semiconductors MPC5566, Reference Manual

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MPC5566 Reference Manual Revision History
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor C-6
Section Separate Input Clock for Registers, For readability, changed from:
• The clock signal dedicated to the registers, however, allows access to the registers even while
the EBI is in the module disable mode.
to:
• The dedicated clock signal allows access to the registers even while the EBI module is in disable
mode.
Chapter 12
“External Bus Interface”
(continued)
Table Signal Function According to EBI Mode Settings:
• Combined two rows labelled Data[16:31] into one row labelled Data[0:21]. Combined three
WE/BE rows: one WE[0:]/BE[0:1] and two WE[2:3]/BE[2:3] to WE/BE[0:3].
• Added the calibration signals: CAL_DATA[0:15], CAL_ADDR[12:30], CAL_OE, CAL_TS,
CAL_RD_WR, CAL_WE/BE[0:1]
• Added footnote: These signals are muxed with the chip select (CS) signals on this device. Use
the pad configuration registers (PCR) in the system integration module (SIU) to configure the
balls to use the address signals
or chip select signals–not both.
• Added footnote: This device is designed to support a 32-bit EBI data bus (DATA[0:31]) and four
write/byte enable signals (WE/BE[0:3]) using the VertiCal assembly.
Renamed the table title from ‘Transaction Sizes Supported by EBI’ to ‘Valid EBI Transaction Sizes
(Number of Bytes)’
Section Size, Alignment, and Packaging on Transfers: Changed first paragraph from:
• Table 12-18 shows the allowed sizes that an internal or external master can request from the EBI.
The behavior of the EBI for request sizes not shown below is undefined. No error signal is
asserted for these erroneous cases.
To:
• Table 12-18 shows the allowed sizes that an internal or external master can request from the EBI.
EBI transfer request sizes not listed in the table are undefined. No error signal is asserted for
these invalid cases.
Changed text in Section Booting from External Memory from:
If code in external memory must write EBI registers, avoid modifying EBI registers while external
accesses are in progress by using the following method:
• Copy to internal SRAM the code that writes to the EBI registers (plus a return branch)
• Branch to internal SRAM to run the code, ending with a branch back to external flash
To:
If code in external memory must write EBI registers, avoid modifying EBI registers while external
accesses are in progress by using the following method:
1. Copy to internal SRAM the code that writes to the EBI registers (plus a return branch)
2. Branch to internal SRAM to run the code, ending with a branch back to external flash
Added section 12.4.1.18 Misaligned Access Support.
Chapter 13
“Flash Memory”
No changes.
Chapter 14
“Internal Static RAM”
Removed L2 designation from the sample code.
Chapter 15
“Fast Ethernet Controller”
Added footnote: “w1c” signifies the bit is cleared by writing 1 to it.” to Figure 15-4 , Ethernet Interrupt
Event Register.
Table C-1. MPC5566 Changes Between Revisions 1 and 2 (continued)
Chapter Description