NXP Semiconductors MPC5566, Reference Manual

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Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
17-36 Freescale Semiconductor
MODE[6] controls if the EMIOS_CSR n [FLAG] is set on both matches or just on the second match (see
Table 17-10 for details).
If subsequent enabled output compares occur on registers A1 and B1, pulses continue to generate,
regardless of the state of the FLAG bit.
At any time, the EMIOS_CCR n [FORCMA] and EMIOS_CCR n [FORCMB] bits allow the software to
force the output flip-flop to the level corresponding to a comparison event in comparator A or B,
respectively. The FLAG bit is not affected by these forced operations.
NOTE
If both registers (A1 and B1) are loaded with the same value, the unified
channel behaves as if a single match on comparator B had occurred; that is,
the output flip-flop is set to the complement of EDPOL bit and the FLAG
bit is set.
Figure 17-23 and Figure 17-24 show how the unified channel can be used to generate a single output pulse
with FLAG bit being set on the second match or on both matches, respectively.
Figure 17-23. Double Action Output Compare with FLAG Set on the Second Match
Selected
counter bus
FLAG
set event
A1 match
0xxxxxxx 0x001000 0x001000 0x001000
Notes:
1
Writing EMIOS_CADR n writes to A1.
2
Writing EMIOS_CBDR n writes to B1.
MODE[6] = 0 B1 match B1 match
0xxxxxxx 0x001100 0x001100 0x001100
A1 match
Update to
A1 and B1
Output
flip-flop
A1 value
1
B1 value
2
A2 value transferred to A1 according to OU n bit.
B2 value transferred to B1 according to OU n bit.
0x000500 0x001000 0x001100 0x001000 0x001100