NXP Semiconductors MPC5566, Reference Manual

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MPC5566 Reference Manual Revision History
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor C-4
Chapter 9
“Enhanced Direct
Memory Access”
In the section on DMA Performance, made this change:
• FROM: removed eDMA Peak Transfer Rate table
• TO: Added an eDMA Peak Transfer Rates table (
Table 9-22 ) with columns that show the effect
of buffering enabled and disabled.
To the TCD Structure diagram, added this footnote to the CITER and BITER fields:
“If channel linking on minor link completion is disabled, TCD bits [161:175] are used to form a 15-bit
CITER field; if channel-to-channel linking is enabled, CITER becomes a 9-bit field.”
Removed the Note: referring to bit 2 in the following tables: EDMA_SERQR, EDMA_CERQR,
EDMA_SEEIR, EDMA_CEEIR, EDMA_CER, EDMA_SSBR, EDMA_CDSBR.
Chapter 10
“Interrupt Controller”
NOTE
Reading the INTC_IACKR acknowledges the interrupt request to the processor and updates the
INTC_CPR[PRI] with the priority of the preempting interrupt request. If the processor recognition of
interrupts is disabled during the LIFO restoration, interrupt requests to the processor can go
undetected. However, since the peripheral or software settable interrupt requests are not cleared,
the peripheral interrupt request to the processor re-asserts when INTC_CPR[PRI] is lower than the
priorities of those peripheral or software settable interrupt requests.
Section 10.5.6, “Selecting Priorities According to Request Rates and Deadlines
Added the acronyms RMS and DMS for ‘rate monotonic scheduling’ and ‘deadline monotonic
scheduling.’
• From: “Reducing the number of priorities does cause some priority inversion which reduces the
processor's ability to meet its deadlines. It also allows easier management of ISRs with similar
deadlines that share a resource. They can be placed at the same priority without any further
priority inversion, and they do not need to use the PCP to access the shared resource”
• To: “Reducing the number of priorities does reduce the processor's ability to meet its deadlines.
However, it also allows easier management of ISRs with similar deadlines that share a resource.
They do not need to use the PCP to access the shared resource.
Throughout the chapter, replaced “priority inversion” with “scheduling inefficiencies”
Added this sentence to “Scheduling a Lower Priority ...” section:
“After generating a software settable interrupt request, the higher priority ISR completes. The lower
priority ISR is scheduled according to its priority. Execution of the higher priority ISR is not resumed
after the completion of the lower priority ISR”
Table 10-9 Combined adjacent reserved areas of memory.
Figure 10-1 INT Block Diagram : Changed key for diagram from: ‘Non-memory mapped logic’
To: Logic not memory-mapped.
Changed footnote 1 from: The total number of interrupt sources is 332, which includes 26 reserved
source and 8 software sources
To: Although N = 329, the total number of interrupts must be a multiple of four. Therefore, the total
number of interrupts is 332: 208 peripheral IRQs, 8 software-configurable IRQs, and 26 reserved
IRQs
Figure 10-3 Program Flow–Software Vector Mode : Added footnote 1 in text frame inside figure that
reads:
N is the maximum number of usable interrupt vectors. which equals 329, and includes 26 reserved
IRQ vectors and eight software-settable IRQ vectors. Because the memory is mapped in four-byte
words, the total number of interrupt vectors must be a multiple of four, therefore one more interrupt
vector exists to complete the word. This results in a total of 332 interrupt vectors. However, interrupt
vector 332 is reserved and not available.
Table C-1. MPC5566 Changes Between Revisions 1 and 2 (continued)
Chapter Description