NXP Semiconductors MPC5566, Reference Manual

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Introduction
MPC5566 Microcontroller Reference Manual, Rev. 2
1-2 Freescale Semiconductor
The DSPIs support pin reduction through hardware serialization and deserialization of timer channels and
general-purpose input/output (GPIO) signals.
The MCU has two on-chip 40-channel enhanced queued dual analog to digital converters (eQADC).
The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration
and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset
control are also found in the SIU. The internal multiplexer submodule (SIU_DISR) provides multiplexing
of eQADC trigger sources, daisy chaining the DSPIs, and external interrupt signal multiplexing.
The Fast Ethernet (FEC) module is a RISC-based controller that supports both 10 and 100 Mbps
Ethernet/IEEE® 802.3 networks and is compatible with three different standard MAC (media access
controller) PHY (physical) interfaces to connect to an external Ethernet bus. The FEC supports the 10 or
100 Mbps MII (media independent interface), and the 10 Mbps-only with a seven-wire interface, which
uses a subset of the MII signals. The upper 16-bits of the 32-bit external bus interface (EBI) are used to
connect to an external Ethernet device. The FEC contains built-in transmit and receive message FIFOs and
DMA support.