NXP Semiconductors MPC5566, Reference Manual

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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 19-37
19.3.3.1 ADC n Control Registers (ADC0_CR and ADC1_CR)
The ADC n control registers (ADC n _CR) are used to configure the on-chip ADCs.
0x0002 ADC Time Stamp Control Register (ADC_TSCR)
1
Write/Read
0x0003 ADC Time Base Counter Register (ADC_TBCR)
1
Write/Read
0x0004 ADC1 Gain Calibration Constant Register (ADC1_GCCR) Write/Read
0x0005 ADC1 Offset Calibration Constant Register (ADC1_OCCR) Write/Read
0x0006–0x00FF Reserved —
1
This register is also accessible by configuration commands sent to the ADC0 command buffer.
Address: 0x0001 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R ADC0
_EN
0 0 0
ADC0_
EM
UX
0 0 0 0 0 0 ADC0_CLK_PS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R ADC1
_EN
0 0 0
ADC1
_
EMUX
0 0 0 0 0 0 ADC1_CLK_PS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
Figure 19-19. ADC n Control Registers (ADC0_CR and ADC1_CR)
Table 19-27. ADC n _CR Field Descriptions
Field Description
0
ADC n _
EN
ADC n enable. Enables ADC n to perform A/D conversions. Refer to Section 19.4.5.1, “Enabling and Disabling the
on-chip ADCs ,” for details.
0 ADC is disabled. Clock supply to ADC0/1 is stopped.
1 ADC is enabled and ready to perform A/D conversions.
Note: The bias generator circuit inside the ADC ceases functioning when both ADC0_EN and ADC1_EN bits are
negated.
Note: Conversion commands sent to a disabled ADC are ignored by the ADC control hardware.
Note: When the ADC n _EN status is changed from asserted to negated, the ADC clock does not stop until it reaches
its low phase.
1–3 Reserved.
Table 19-26. ADC1 Registers (continued)