NXP Semiconductors MPC5566, Reference Manual

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Enhanced Direct Memory Access (eDMA)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 9-37
Table 9-20 presents a peak transfer rate comparison, measured in MBs per second where the
internal-SRAM-to-internal-SRAM transfers occur at the core’s datapath width; that is, either 32- or 64-bits
per access. For all transfers involving the slave bus, 32-bit transfer sizes are used. In all cases, the transfer
rate includes the time to read the source plus the time to write the destination.
The second performance metric is a measure of the number of DMA requests that can be serviced in a
given amount of time. For this metric, it is assumed the peripheral request causes the channel to move a
single slave-mapped operand to/from internal SRAM. The same timing assumptions used in the previous
example apply to this calculation. In particular, this metric also reflects the time required to activate the
channel. The eDMA design supports the following hardware service request sequence:
• Cycle 1: eDMA peripheral request is asserted.
• Cycle 2: The eDMA peripheral request is registered locally in the eDMA module and
qualified. (TCD.START bit initiated requests start at this point with the registering
of the slave write to TCD bit 255).
• Cycle 3: Channel arbitration begins.
• Cycle 4: Channel arbitration completes. The transfer control descriptor local memory read is
initiated.
• Cycle 5–6: The first two parts of the activated channel’s TCD is read from the local memory.
The memory width to the eDMA engine is 64 bits, so the entire descriptor can be
accessed in four cycles.
Table 9-20. eDMA Peak Transfer Rates (MB/Sec)
System Speed,
Transfer Size Internal SRAM-to-
Internal SRAM
32-Bit Slave-to-
Internal SRAM
Internal SRAM-to-
32-Bit Slave
(buffering disabled)
Internal SRAM-to-
32-Bit Slave
(buffering enabled)
66.7 MHz, 32 bit 66.7 66.7 53.3 88.7
66.7 MHz, 64 bit 133.3 66.7 53.3 88.7
66.7 MHz, 256 bit
1
1
A 256-bit transfer occurs as a burst of four 64-bit beats.
213.4 N/A
2
2
Not applicable: burst access to a slave port is not supported.
N/A
2
N/A
2
83.3 MHz, 32 bit 83.3 83.3 66.7 110.8
83.3 MHz, 64 bit 166.7 83.3 66.7 110.8
83.3 MHz, 256 bit
1
266.6 N/A
2
N/A
2
N/A
2
100.0 MHz, 32 bit 100.0 100.0 80.0 133.0
100.0 MHz, 64 bit 200.0 100.0 80.0 133.0
100.0 MHz, 256 bit
1
320.0 N/A
2
N/A
2
N/A
2
132.0 MHz, 32 bit 132.0 132.0 105.6 175.6
132.0 MHz, 64 bit 264.0 132.0 105.6 175.6
132.0 MHz, 256 bit
1
422.4 N/A
2
N/A
2
N/A
2