NXP Semiconductors MPC5566, Reference Manual

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MPC5566 Register Map
MPC5566 Microcontroller Reference Manual, Rev. 2
A-56 Freescale Semiconductor
Reserved — — Base + (0x00B0–0x00B3)
SSI control register EQADC_SSICR 32-bit Base + 0x00B4
SSI receive data register EQADC_SSIRDR 32-bit Base + 0x00B8
Reserved — — Base + (0x00BC–0x00FF)
CFIFO 0 register 0 EQADC_CF0R0 32-bit Base + 0x0100
CFIFO 0 register 1 EQADC_CF0R1 32-bit Base + 0x0104
CFIFO 0 register 2 EQADC_CF0R2 32-bit Base + 0x0108
CFIFO 0 register 3 EQADC_CF0R3 32-bit Base + 0x010C
Reserved — — Base + (0x0110–0x013F)
CFIFO 1 register 0 EQADC_CF1R0 32-bit Base + 0x0140
CFIFO 1 register 1 EQADC_CF1R1 32-bit Base + 0x0144
CFIFO 1 register 2 EQADC_CF1R2 32-bit Base + 0x0148
CFIFO 1 register 3 EQADC_CF1R3 32-bit Base + 0x014C
Reserved — — Base + (0x0150–0x017F)
CFIFO 2 register 0 EQADC_CF2R0 32-bit Base + 0x0180
CFIFO 2 register 1 EQADC_CF2R1 32-bit Base + 0x0184
CFIFO 2 register 2 EQADC_CF2R2 32-bit Base + 0x0188
CFIFO 2 register 3 EQADC_CF2R3 32-bit Base + 0x018C
Reserved — — Base + (0x0190–0x01BF)
CFIFO 3 register 0 EQADC_CF3R0 32-bit Base + 0x01C0
CFIFO 3 register 1 EQADC_CF3R1 32-bit Base + 0x01C4
CFIFO 3 register 2 EQADC_CF3R2 32-bit Base + 0x01C8
CFIFO 3 register 3 EQADC_CF3R3 32-bit Base + 0x01CC
Reserved — — Base + (0x01D0–0x01FF)
CFIFO 4 register 0 EQADC_CF4R0 32-bit Base + 0x0200
CFIFO 4 register 1 EQADC_CF4R1 32-bit Base + 0x0204
CFIFO 4 register 2 EQADC_CF4R2 32-bit Base + 0x0208
CFIFO 4 register 3 EQADC_CF4R3 32-bit Base + 0x020C
Reserved — — Base + (0x0210–0x023F)
Table A-2. MPC5566 Detailed Register Map (continued)
Register Description Register Name
Used
Size
Address