NXP Semiconductors MPC5566, Reference Manual

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MPC5566 Register Map
MPC5566 Microcontroller Reference Manual, Rev. 2
A-54 Freescale Semiconductor
Upper 32 bits of group hash table GAUR 32-bit Base + 0x0120
Lower 32 bits of group hash table GALR 32-bit Base + 0x0124
Transmit FIFO watermark TFWR 32-bit Base + 0x0144
FIFO receive bound register FRBR 32-bit Base + 0x014C
FIFO receive FIFO start registers FRSR 32-bit Base + 0x0150
Pointer to receive descriptor ring ERDSR 32-bit Base + 0x0180
Pointer to transmit descriptor ring ETDSR 32-bit Base + 0x0184
Maximum receive buffer size EMRBR 32-bit Base + 0x0188
MIB block counters MIB FFF4_C200
Reserved — — Base + 0xFFF0_8000
Reserved — — Base + 0xFFF1_0000
Enhanced Queued Analog-to-Digital Converter (eQADC)
Chapter 18, “Enhanced Queued Analog-to-Digital Converter (eQADC) ”
0xFFF8_0000
Module configuration register EQADC_MCR 32-bit Base + 0x0000
Reserved — — Base + (0x0004–0x0007)
Null message send format register EQADC_NMSFR 32-bit Base + 0x0008
External trigger digital filter register EQADC_ETDFR 32-bit Base + 0x000C
CFIFO push register 0 EQADC_CFPR0 32-bit Base + 0x0010
CFIFO push register 1 EQADC_CFPR1 32-bit Base + 0x0014
CFIFO push register 2 EQADC_CFPR2 32-bit Base + 0x0018
CFIFO push register 3 EQADC_CFPR3 32-bit Base + 0x001C
CFIFO push register 4 EQADC_CFPR4 32-bit Base + 0x0020
CFIFO push register 5 EQADC_CFPR5 32-bit Base + 0x0024
Reserved — — Base + (0x0028–0x002F)
Result FIFO pop register 0 EQADC_RFPR0 32-bit Base + 0x0030
Result FIFO pop register 1 EQADC_RFPR1 32-bit Base + 0x0034
Result FIFO pop register 2 EQADC_RFPR2 32-bit Base + 0x0038
Result FIFO pop register 3 EQADC_RFPR3 32-bit Base + 0x003C
Result FIFO pop register 4 EQADC_RFPR4 32-bit Base + 0x0040
Result FIFO pop register 5 EQADC_RFPR5 32-bit Base + 0x0044
Reserved — — Base + (0x0048–0x004F)
Table A-2. MPC5566 Detailed Register Map (continued)
Register Description Register Name
Used
Size
Address